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Add left shift

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llvm-svn: 70747
This commit is contained in:
Anton Korobeynikov 2009-05-03 13:13:17 +00:00
parent d9b4143e47
commit 1f80bde7ad
3 changed files with 17 additions and 5 deletions
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12
lib/Target/MSP430/MSP430ISelLowering.cpp
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@ -68,6 +68,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
setTruncStoreAction(MVT::i16, MVT::i8, Expand); setTruncStoreAction(MVT::i16, MVT::i8, Expand);
setOperationAction(ISD::SRA, MVT::i16, Custom); setOperationAction(ISD::SRA, MVT::i16, Custom);
setOperationAction(ISD::SHL, MVT::i16, Custom);
setOperationAction(ISD::RET, MVT::Other, Custom); setOperationAction(ISD::RET, MVT::Other, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
setOperationAction(ISD::BR_CC, MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::Other, Expand);
@ -82,6 +83,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
case ISD::SHL: // FALLTHROUGH
case ISD::SRA: return LowerShifts(Op, DAG); case ISD::SRA: return LowerShifts(Op, DAG);
case ISD::RET: return LowerRET(Op, DAG); case ISD::RET: return LowerRET(Op, DAG);
case ISD::CALL: return LowerCALL(Op, DAG); case ISD::CALL: return LowerCALL(Op, DAG);
@ -416,12 +418,14 @@ MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
SDValue MSP430TargetLowering::LowerShifts(SDValue Op, SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) {
assert(Op.getOpcode() == ISD::SRA && "Only SRA is currently supported."); unsigned Opc = Op.getOpcode();
assert((Opc == ISD::SRA || ISD::SHL) &&
"Only SRA and SHL are currently supported.");
SDNode* N = Op.getNode(); SDNode* N = Op.getNode();
MVT VT = Op.getValueType(); MVT VT = Op.getValueType();
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
// We currently only lower SRA of constant argument. // We currently only lower shifts of constant argument.
if (!isa<ConstantSDNode>(N->getOperand(1))) if (!isa<ConstantSDNode>(N->getOperand(1)))
return SDValue(); return SDValue();
@ -432,7 +436,8 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
// E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
SDValue Victim = N->getOperand(0); SDValue Victim = N->getOperand(0);
while (ShiftAmount--) while (ShiftAmount--)
Victim = DAG.getNode(MSP430ISD::RRA, dl, VT, Victim); Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
dl, VT, Victim);
return Victim; return Victim;
} }
@ -560,6 +565,7 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
default: return NULL; default: return NULL;
case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
case MSP430ISD::RRA: return "MSP430ISD::RRA"; case MSP430ISD::RRA: return "MSP430ISD::RRA";
case MSP430ISD::RLA: return "MSP430ISD::RRA";
case MSP430ISD::CALL: return "MSP430ISD::CALL"; case MSP430ISD::CALL: return "MSP430ISD::CALL";
case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
case MSP430ISD::BRCOND: return "MSP430ISD::BRCOND"; case MSP430ISD::BRCOND: return "MSP430ISD::BRCOND";

4
lib/Target/MSP430/MSP430ISelLowering.h
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@ -27,8 +27,8 @@ namespace llvm {
/// Return with a flag operand. Operand 0 is the chain operand. /// Return with a flag operand. Operand 0 is the chain operand.
RET_FLAG, RET_FLAG,
/// Y = RRA X, rotate right arithmetically /// Y = R{R,L}A X, rotate right (left) arithmetically
RRA, RRA, RLA,
/// CALL/TAILCALL - These operations represent an abstract call /// CALL/TAILCALL - These operations represent an abstract call
/// instruction, which includes a bunch of information. /// instruction, which includes a bunch of information.

6
lib/Target/MSP430/MSP430InstrInfo.td
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@ -41,6 +41,7 @@ def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;
def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>; def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call, def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
@ -591,6 +592,11 @@ def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
[(set GR16:$dst, (MSP430rra GR16:$src)), [(set GR16:$dst, (MSP430rra GR16:$src)),
(implicit SRW)]>; (implicit SRW)]>;
def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
"rla.w\t$dst",
[(set GR16:$dst, (MSP430rla GR16:$src)),
(implicit SRW)]>;
def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src), def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
"sxt\t$dst", "sxt\t$dst",
[(set GR16:$dst, (sext_inreg GR16:$src, i8)), [(set GR16:$dst, (sext_inreg GR16:$src, i8)),