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X86: Fix LowerBUILD_VECTORAsVariablePermute for case Src is smaller than Indices
Summary: As RKSimon suggested in pr35820, in the case that Src is smaller in bit-size than Indices, need to widen Src to avoid type mismatch. Fixes pr35820 Reviewers: RKSimon, craig.topper Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41865 llvm-svn: 322272
This commit is contained in:
Zvi Rackover
parent
132ad3d36c
commit
2024c53178
@ -7867,6 +7867,11 @@ LowerBUILD_VECTORAsVariablePermute(SDValue V, SelectionDAG &DAG,
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IndicesVT = MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits()),
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VT.getVectorNumElements());
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IndicesVec = DAG.getZExtOrTrunc(IndicesVec, SDLoc(IndicesVec), IndicesVT);
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if (SrcVec.getValueSizeInBits() < IndicesVT.getSizeInBits()) {
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SrcVec =
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DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(SrcVec), VT, DAG.getUNDEF(VT),
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SrcVec, DAG.getIntPtrConstant(0, SDLoc(SrcVec)));
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}
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return DAG.getNode(VT == MVT::v16i8 ? X86ISD::PSHUFB : X86ISD::VPERMV,
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SDLoc(V), VT, IndicesVec, SrcVec);
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}
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@ -1277,3 +1277,183 @@ define <8 x float> @var_shuffle_v8f32(<8 x float> %v, <8 x i32> %indices) nounwi
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%ret7 = insertelement <8 x float> %ret6, float %v7, i32 7
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ret <8 x float> %ret7
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}
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define <8 x i32> @pr35820(<4 x i32> %v, <8 x i32> %indices) unnamed_addr nounwind {
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; AVX1-LABEL: pr35820:
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; AVX1: # %bb.0: # %entry
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; AVX1-NEXT: vpextrq $1, %xmm1, %r8
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; AVX1-NEXT: movq %r8, %r10
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; AVX1-NEXT: shrq $30, %r10
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; AVX1-NEXT: vmovq %xmm1, %r9
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; AVX1-NEXT: movq %r9, %rsi
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; AVX1-NEXT: shrq $30, %rsi
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; AVX1-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
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; AVX1-NEXT: andl $3, %r9d
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; AVX1-NEXT: andl $12, %esi
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; AVX1-NEXT: andl $3, %r8d
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; AVX1-NEXT: andl $12, %r10d
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0
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; AVX1-NEXT: vpextrq $1, %xmm0, %rax
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; AVX1-NEXT: movq %rax, %rdi
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; AVX1-NEXT: shrq $30, %rdi
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; AVX1-NEXT: vmovq %xmm0, %rcx
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; AVX1-NEXT: movq %rcx, %rdx
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; AVX1-NEXT: shrq $30, %rdx
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; AVX1-NEXT: andl $3, %ecx
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; AVX1-NEXT: andl $12, %edx
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; AVX1-NEXT: andl $3, %eax
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; AVX1-NEXT: andl $12, %edi
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; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX1-NEXT: vpinsrd $1, -24(%rsp,%rdx), %xmm0, %xmm0
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; AVX1-NEXT: vpinsrd $2, -24(%rsp,%rax,4), %xmm0, %xmm0
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; AVX1-NEXT: vpinsrd $3, -24(%rsp,%rdi), %xmm0, %xmm0
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; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; AVX1-NEXT: vpinsrd $1, -24(%rsp,%rsi), %xmm1, %xmm1
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; AVX1-NEXT: vpinsrd $2, -24(%rsp,%r8,4), %xmm1, %xmm1
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; AVX1-NEXT: vpinsrd $3, -24(%rsp,%r10), %xmm1, %xmm1
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; INT256-LABEL: pr35820:
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; INT256: # %bb.0: # %entry
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; INT256-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
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; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; INT256-NEXT: retq
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entry:
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%tmp1 = extractelement <8 x i32> %indices, i32 0
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%vecext2.8 = extractelement <4 x i32> %v, i32 %tmp1
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%tmp2 = extractelement <8 x i32> %indices, i32 1
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%vecext2.9 = extractelement <4 x i32> %v, i32 %tmp2
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%tmp3 = extractelement <8 x i32> %indices, i32 2
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%vecext2.10 = extractelement <4 x i32> %v, i32 %tmp3
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%tmp4 = extractelement <8 x i32> %indices, i32 3
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%vecext2.11 = extractelement <4 x i32> %v, i32 %tmp4
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%tmp5 = extractelement <8 x i32> %indices, i32 4
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%vecext2.12 = extractelement <4 x i32> %v, i32 %tmp5
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%tmp6 = extractelement <8 x i32> %indices, i32 5
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%vecext2.13 = extractelement <4 x i32> %v, i32 %tmp6
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%tmp7 = extractelement <8 x i32> %indices, i32 6
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%vecext2.14 = extractelement <4 x i32> %v, i32 %tmp7
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%tmp8 = extractelement <8 x i32> %indices, i32 7
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%vecext2.15 = extractelement <4 x i32> %v, i32 %tmp8
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%tmp9 = insertelement <8 x i32> undef, i32 %vecext2.8, i32 0
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%tmp10 = insertelement <8 x i32> %tmp9, i32 %vecext2.9, i32 1
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%tmp11 = insertelement <8 x i32> %tmp10, i32 %vecext2.10, i32 2
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%tmp12 = insertelement <8 x i32> %tmp11, i32 %vecext2.11, i32 3
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%tmp13 = insertelement <8 x i32> %tmp12, i32 %vecext2.12, i32 4
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%tmp14 = insertelement <8 x i32> %tmp13, i32 %vecext2.13, i32 5
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%tmp15 = insertelement <8 x i32> %tmp14, i32 %vecext2.14, i32 6
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%tmp16 = insertelement <8 x i32> %tmp15, i32 %vecext2.15, i32 7
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ret <8 x i32> %tmp16
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}
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define <8 x float> @pr35820_float(<4 x float> %v, <8 x i32> %indices) unnamed_addr nounwind {
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; AVX1-LABEL: pr35820_float:
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; AVX1: # %bb.0: # %entry
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; AVX1-NEXT: vpextrq $1, %xmm1, %r8
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; AVX1-NEXT: movq %r8, %r10
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; AVX1-NEXT: shrq $30, %r10
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; AVX1-NEXT: vmovq %xmm1, %r9
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; AVX1-NEXT: movq %r9, %rdx
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; AVX1-NEXT: shrq $30, %rdx
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; AVX1-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
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; AVX1-NEXT: andl $3, %r9d
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; AVX1-NEXT: andl $12, %edx
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; AVX1-NEXT: andl $3, %r8d
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; AVX1-NEXT: andl $12, %r10d
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0
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; AVX1-NEXT: vpextrq $1, %xmm0, %rax
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; AVX1-NEXT: movq %rax, %rdi
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; AVX1-NEXT: shrq $30, %rdi
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; AVX1-NEXT: vmovq %xmm0, %rcx
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; AVX1-NEXT: movq %rcx, %rsi
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; AVX1-NEXT: shrq $30, %rsi
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; AVX1-NEXT: andl $3, %ecx
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; AVX1-NEXT: andl $12, %esi
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; AVX1-NEXT: andl $3, %eax
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; AVX1-NEXT: andl $12, %edi
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; AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
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; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
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; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
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; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
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; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; INT256-LABEL: pr35820_float:
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; INT256: # %bb.0: # %entry
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; INT256-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
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; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; INT256-NEXT: retq
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entry:
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%tmp1 = extractelement <8 x i32> %indices, i32 0
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%vecext2.8 = extractelement <4 x float> %v, i32 %tmp1
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%tmp2 = extractelement <8 x i32> %indices, i32 1
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%vecext2.9 = extractelement <4 x float> %v, i32 %tmp2
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%tmp3 = extractelement <8 x i32> %indices, i32 2
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%vecext2.10 = extractelement <4 x float> %v, i32 %tmp3
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%tmp4 = extractelement <8 x i32> %indices, i32 3
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%vecext2.11 = extractelement <4 x float> %v, i32 %tmp4
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%tmp5 = extractelement <8 x i32> %indices, i32 4
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%vecext2.12 = extractelement <4 x float> %v, i32 %tmp5
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%tmp6 = extractelement <8 x i32> %indices, i32 5
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%vecext2.13 = extractelement <4 x float> %v, i32 %tmp6
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%tmp7 = extractelement <8 x i32> %indices, i32 6
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%vecext2.14 = extractelement <4 x float> %v, i32 %tmp7
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%tmp8 = extractelement <8 x i32> %indices, i32 7
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%vecext2.15 = extractelement <4 x float> %v, i32 %tmp8
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%tmp9 = insertelement <8 x float> undef, float %vecext2.8, i32 0
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%tmp10 = insertelement <8 x float> %tmp9, float %vecext2.9, i32 1
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%tmp11 = insertelement <8 x float> %tmp10, float %vecext2.10, i32 2
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%tmp12 = insertelement <8 x float> %tmp11, float %vecext2.11, i32 3
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%tmp13 = insertelement <8 x float> %tmp12, float %vecext2.12, i32 4
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%tmp14 = insertelement <8 x float> %tmp13, float %vecext2.13, i32 5
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%tmp15 = insertelement <8 x float> %tmp14, float %vecext2.14, i32 6
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%tmp16 = insertelement <8 x float> %tmp15, float %vecext2.15, i32 7
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ret <8 x float> %tmp16
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}
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define <4 x i32> @big_source(<8 x i32> %v, <4 x i32> %indices) unnamed_addr nounwind {
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; AVX-LABEL: big_source:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: pushq %rbp
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; AVX-NEXT: movq %rsp, %rbp
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; AVX-NEXT: andq $-32, %rsp
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; AVX-NEXT: subq $64, %rsp
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; AVX-NEXT: vmovq %xmm1, %rax
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; AVX-NEXT: movq %rax, %rcx
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; AVX-NEXT: shrq $30, %rcx
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; AVX-NEXT: andl $28, %ecx
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; AVX-NEXT: vpextrq $1, %xmm1, %rdx
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; AVX-NEXT: movq %rdx, %rsi
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; AVX-NEXT: sarq $32, %rsi
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; AVX-NEXT: andl $7, %eax
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; AVX-NEXT: andl $7, %edx
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; AVX-NEXT: vmovaps %ymm0, (%rsp)
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; AVX-NEXT: andl $7, %esi
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; AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: vpinsrd $1, (%rsp,%rcx), %xmm0, %xmm0
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; AVX-NEXT: vpinsrd $2, (%rsp,%rdx,4), %xmm0, %xmm0
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; AVX-NEXT: vpinsrd $3, (%rsp,%rsi,4), %xmm0, %xmm0
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; AVX-NEXT: movq %rbp, %rsp
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; AVX-NEXT: popq %rbp
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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entry:
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%tmp1 = extractelement <4 x i32> %indices, i32 0
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%vecext2.8 = extractelement <8 x i32> %v, i32 %tmp1
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%tmp2 = extractelement <4 x i32> %indices, i32 1
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%vecext2.9 = extractelement <8 x i32> %v, i32 %tmp2
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%tmp3 = extractelement <4 x i32> %indices, i32 2
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%vecext2.10 = extractelement <8 x i32> %v, i32 %tmp3
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%tmp4 = extractelement <4 x i32> %indices, i32 3
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%vecext2.11 = extractelement <8 x i32> %v, i32 %tmp4
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%tmp9 = insertelement <4 x i32> undef, i32 %vecext2.8, i32 0
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%tmp10 = insertelement <4 x i32> %tmp9, i32 %vecext2.9, i32 1
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%tmp11 = insertelement <4 x i32> %tmp10, i32 %vecext2.10, i32 2
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%tmp12 = insertelement <4 x i32> %tmp11, i32 %vecext2.11, i32 3
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ret <4 x i32> %tmp12
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}
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