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Hexagon: Remove duplicate instructions to handle global/immediate values
for absolute/absolute-set addressing modes. llvm-svn: 180120
This commit is contained in:
Jyotsna Verma
parent
d8a8d1d02f
commit
20903a7aba
@ -746,11 +746,6 @@ bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
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case Hexagon::STrib_abs_cdnPt_nv_V4:
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case Hexagon::STrib_abs_cNotPt_nv_V4:
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case Hexagon::STrib_abs_cdnNotPt_nv_V4:
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case Hexagon::STrib_imm_abs_nv_V4:
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case Hexagon::STrib_imm_abs_cPt_nv_V4:
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case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
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case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
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case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
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// Store Halfword
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case Hexagon::STrih_nv_V4:
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@ -784,11 +779,6 @@ bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
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case Hexagon::STrih_abs_cdnPt_nv_V4:
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case Hexagon::STrih_abs_cNotPt_nv_V4:
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case Hexagon::STrih_abs_cdnNotPt_nv_V4:
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case Hexagon::STrih_imm_abs_nv_V4:
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case Hexagon::STrih_imm_abs_cPt_nv_V4:
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case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
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case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
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case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
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// Store Word
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case Hexagon::STriw_nv_V4:
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@ -822,11 +812,6 @@ bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
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case Hexagon::STriw_abs_cdnPt_nv_V4:
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case Hexagon::STriw_abs_cNotPt_nv_V4:
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case Hexagon::STriw_abs_cdnNotPt_nv_V4:
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case Hexagon::STriw_imm_abs_nv_V4:
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case Hexagon::STriw_imm_abs_cPt_nv_V4:
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case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
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case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
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case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
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return true;
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}
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}
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@ -209,99 +209,25 @@ def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
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//===----------------------------------------------------------------------===//
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// LD +
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//===----------------------------------------------------------------------===//
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//
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// These absolute set addressing mode instructions accept immediate as
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// an operand. We have duplicated these patterns to take global address.
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//===----------------------------------------------------------------------===//
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// Template class for load instructions with Absolute set addressing mode.
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//===----------------------------------------------------------------------===//
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let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
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validSubTargets = HasV4SubT in {
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def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
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validSubTargets = HasV4SubT in
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class T_LD_abs_set<string mnemonic, RegisterClass RC>:
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LDInst2<(outs RC:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memd($dst2=##$addr)",
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"$dst1 = "#mnemonic#"($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memb(Re=#U6)
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def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memb($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
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def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
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def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
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def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
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def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
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def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
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// Rd=memh(Re=#U6)
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def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memh($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memub(Re=#U6)
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def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memub($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memuh(Re=#U6)
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def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memuh($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memw(Re=#U6)
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def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = memw($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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}
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// Following patterns are defined for absolute set addressing mode
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// instruction which take global address as operand.
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let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
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validSubTargets = HasV4SubT in {
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def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memd($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memb(Re=#U6)
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def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memb($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memh(Re=#U6)
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def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memh($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memub(Re=#U6)
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def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memub($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memuh(Re=#U6)
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def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memuh($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memw(Re=#U6)
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def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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(ins globaladdressExt:$addr),
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"$dst1 = memw($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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}
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// multiclass for load instructions with base + register offset
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// addressing mode
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@ -527,75 +453,26 @@ def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
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// ST +
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//===----------------------------------------------------------------------===//
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///
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/// Assumptions::: ****** DO NOT IGNORE ********
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/// 1. Make sure that in post increment store, the zero'th operand is always the
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/// post increment operand.
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/// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
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/// last operand.
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///
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// memd(Re=#U)=Rtt
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let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
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def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins DoubleRegs:$src1, u0AlwaysExt:$src2),
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"memd($dst1=##$src2) = $src1",
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//===----------------------------------------------------------------------===//
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// Template class for store instructions with Absolute set addressing mode.
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//===----------------------------------------------------------------------===//
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let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
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class T_ST_abs_set<string mnemonic, RegisterClass RC>:
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STInst2<(outs IntRegs:$dst1),
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(ins RC:$src1, u0AlwaysExt:$src2),
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mnemonic#"($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memb(Re=#U)=Rs
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def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, u0AlwaysExt:$src2),
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"memb($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memh(Re=#U)=Rs
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def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, u0AlwaysExt:$src2),
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"memh($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memw(Re=#U)=Rs
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def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, u0AlwaysExt:$src2),
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"memw($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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}
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// memd(Re=#U)=Rtt
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let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
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def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins DoubleRegs:$src1, globaladdressExt:$src2),
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"memd($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memb(Re=#U)=Rs
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def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, globaladdressExt:$src2),
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"memb($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memh(Re=#U)=Rs
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def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, globaladdressExt:$src2),
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"memh($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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// memw(Re=#U)=Rs
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def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
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(ins IntRegs:$src1, globaladdressExt:$src2),
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"memw($dst1=##$src2) = $src1",
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[]>,
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Requires<[HasV4T]>;
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}
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def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
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def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
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def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
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def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
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//===----------------------------------------------------------------------===//
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// multiclass for store instructions with base + register offset addressing
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// mode
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//===----------------------------------------------------------------------===//
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multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let isPredicatedNew = isPredNew in
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@ -2771,7 +2648,7 @@ multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME#_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdressExt:$absaddr, RC: $src2),
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(ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"(##$absaddr) = $src2",
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[]>,
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@ -2791,7 +2668,7 @@ multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
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let opExtendable = 0, isPredicable = 1 in
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def NAME#_V4 : STInst2<(outs),
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(ins globaladdressExt:$absaddr, RC:$src),
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(ins u0AlwaysExt:$absaddr, RC:$src),
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mnemonic#"(##$absaddr) = $src",
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[]>,
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Requires<[HasV4T]>;
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@ -2807,7 +2684,7 @@ multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME#_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, globaladdressExt:$absaddr, RC: $src2),
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(ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"(##$absaddr) = $src2.new",
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[]>,
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@ -2827,7 +2704,7 @@ multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
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let opExtendable = 0, isPredicable = 1 in
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def NAME#_nv_V4 : NVInst_V4<(outs),
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(ins globaladdressExt:$absaddr, RC:$src),
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(ins u0AlwaysExt:$absaddr, RC:$src),
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mnemonic#"(##$absaddr) = $src.new",
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[]>,
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Requires<[HasV4T]>;
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@ -2840,16 +2717,19 @@ multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
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}
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let addrMode = Absolute in {
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let accessSize = ByteAccess in
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defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
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ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
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let accessSize = HalfWordAccess in
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defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
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ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
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let accessSize = WordAccess in
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defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
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ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
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let isNVStorable = 0 in
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let accessSize = DoubleWordAccess, isNVStorable = 0 in
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defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
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}
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@ -2976,7 +2856,7 @@ multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME : LDInst2<(outs RC:$dst),
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(ins PredRegs:$src1, globaladdressExt:$absaddr),
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(ins PredRegs:$src1, u0AlwaysExt:$absaddr),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#"$dst = "#mnemonic#"(##$absaddr)",
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[]>,
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@ -2996,7 +2876,7 @@ multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
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let opExtendable = 1, isPredicable = 1 in
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def NAME#_V4 : LDInst2<(outs RC:$dst),
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(ins globaladdressExt:$absaddr),
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(ins u0AlwaysExt:$absaddr),
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"$dst = "#mnemonic#"(##$absaddr)",
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[]>,
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Requires<[HasV4T]>;
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@ -3009,33 +2889,37 @@ multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
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}
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let addrMode = Absolute in {
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let accessSize = ByteAccess in {
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defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
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defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
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}
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let accessSize = HalfWordAccess in {
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defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
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defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
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}
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let accessSize = WordAccess in
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defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
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let accessSize = DoubleWordAccess in
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defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
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}
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let Predicates = [HasV4T], AddedComplexity = 30 in
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let Predicates = [HasV4T], AddedComplexity = 30 in {
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def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
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(LDriw_abs_V4 tglobaladdr: $absaddr)>;
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let Predicates = [HasV4T], AddedComplexity=30 in
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def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
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(LDrib_abs_V4 tglobaladdr:$absaddr)>;
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let Predicates = [HasV4T], AddedComplexity=30 in
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def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
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(LDriub_abs_V4 tglobaladdr:$absaddr)>;
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let Predicates = [HasV4T], AddedComplexity=30 in
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def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
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(LDrih_abs_V4 tglobaladdr:$absaddr)>;
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let Predicates = [HasV4T], AddedComplexity=30 in
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def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
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(LDriuh_abs_V4 tglobaladdr:$absaddr)>;
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}
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//===----------------------------------------------------------------------===//
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// multiclass for load instructions with GP-relative addressing mode.
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@ -3240,170 +3124,35 @@ defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
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defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
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defm STriw_ind : ST_indirect_lo<"memw", store>;
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// Store - absolute addressing mode: These instruction take constant
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// value as the extended operand.
|
||||
multiclass ST_absimm<string OpcStr> {
|
||||
let isExtended = 1, opExtendable = 0, isPredicable = 1,
|
||||
validSubTargets = HasV4SubT in
|
||||
def _abs_V4 : STInst2<(outs),
|
||||
(ins u0AlwaysExt:$src1, IntRegs:$src2),
|
||||
!strconcat(OpcStr, "(##$src1) = $src2"),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isExtended = 1, opExtendable = 1, isPredicated = 1,
|
||||
validSubTargets = HasV4SubT in {
|
||||
def _abs_cPt_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if ($src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_cNotPt_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if (!$src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_cdnPt_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if ($src1.new)",
|
||||
!strconcat(OpcStr, "(##$src2) = $src3")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_cdnNotPt_V4 : STInst2<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if (!$src1.new)",
|
||||
!strconcat(OpcStr, "(##$src2) = $src3")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
|
||||
let isExtended = 1, opExtendable = 0, mayStore = 1, isNVStore = 1,
|
||||
validSubTargets = HasV4SubT in
|
||||
def _abs_nv_V4 : NVInst_V4<(outs),
|
||||
(ins u0AlwaysExt:$src1, IntRegs:$src2),
|
||||
!strconcat(OpcStr, "(##$src1) = $src2.new"),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isExtended = 1, opExtendable = 1, mayStore = 1, isPredicated = 1,
|
||||
isNVStore = 1, validSubTargets = HasV4SubT in {
|
||||
def _abs_cPt_nv_V4 : NVInst_V4<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if ($src1)",
|
||||
!strconcat(OpcStr, "(##$src2) = $src3.new")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_cNotPt_nv_V4 : NVInst_V4<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if (!$src1)",
|
||||
!strconcat(OpcStr, "(##$src2) = $src3.new")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_cdnPt_nv_V4 : NVInst_V4<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if ($src1.new)",
|
||||
!strconcat(OpcStr, "(##$src2) = $src3.new")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_cdnNotPt_nv_V4 : NVInst_V4<(outs),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
|
||||
!strconcat("if (!$src1.new)",
|
||||
!strconcat(OpcStr, "(##$src2) = $src3.new")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
}
|
||||
|
||||
defm STrib_imm : ST_absimm<"memb">;
|
||||
defm STrih_imm : ST_absimm<"memh">;
|
||||
defm STriw_imm : ST_absimm<"memw">;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity = 30 in {
|
||||
def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
|
||||
(STrib_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
|
||||
(STrib_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
|
||||
|
||||
def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
|
||||
(STrih_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
|
||||
(STrih_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
|
||||
|
||||
def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
|
||||
(STriw_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
|
||||
(STriw_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
|
||||
}
|
||||
|
||||
// Load - absolute addressing mode: These instruction take constant
|
||||
// value as the extended operand
|
||||
|
||||
multiclass LD_absimm<string OpcStr> {
|
||||
let isExtended = 1, opExtendable = 1, isPredicable = 1,
|
||||
validSubTargets = HasV4SubT in
|
||||
def _abs_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins u0AlwaysExt:$src),
|
||||
!strconcat("$dst = ",
|
||||
!strconcat(OpcStr, "(##$src)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isExtended = 1, opExtendable = 2, isPredicated = 1,
|
||||
validSubTargets = HasV4SubT in {
|
||||
def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2),
|
||||
!strconcat("if ($src1) $dst = ",
|
||||
!strconcat(OpcStr, "(##$src2)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2),
|
||||
!strconcat("if (!$src1) $dst = ",
|
||||
!strconcat(OpcStr, "(##$src2)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2),
|
||||
!strconcat("if ($src1.new) $dst = ",
|
||||
!strconcat(OpcStr, "(##$src2)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, u0AlwaysExt:$src2),
|
||||
!strconcat("if (!$src1.new) $dst = ",
|
||||
!strconcat(OpcStr, "(##$src2)")),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
}
|
||||
|
||||
defm LDrib_imm : LD_absimm<"memb">;
|
||||
defm LDriub_imm : LD_absimm<"memub">;
|
||||
defm LDrih_imm : LD_absimm<"memh">;
|
||||
defm LDriuh_imm : LD_absimm<"memuh">;
|
||||
defm LDriw_imm : LD_absimm<"memw">;
|
||||
|
||||
let Predicates = [HasV4T], AddedComplexity = 30 in {
|
||||
def : Pat<(i32 (load u0AlwaysExtPred:$src)),
|
||||
(LDriw_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
(LDriw_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
|
||||
def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
|
||||
(LDrib_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
(LDrib_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
|
||||
def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
|
||||
(LDriub_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
(LDriub_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
|
||||
def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
|
||||
(LDrih_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
(LDrih_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
|
||||
def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
|
||||
(LDriuh_imm_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
(LDriuh_abs_V4 u0AlwaysExtPred:$src)>;
|
||||
}
|
||||
|
||||
// Indexed store double word - global address.
|
||||
// Indexed store word - global address.
|
||||
// memw(Rs+#u6:2)=#S8
|
||||
let AddedComplexity = 10 in
|
||||
def STriw_offset_ext_V4 : STInst<(outs),
|
||||
|
||||
18
test/CodeGen/Hexagon/absimm.ll
Normal file
18
test/CodeGen/Hexagon/absimm.ll
Normal file
@ -0,0 +1,18 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; Check that we generate absolute addressing mode instructions
|
||||
; with immediate value.
|
||||
|
||||
define i32 @f1(i32 %i) nounwind {
|
||||
; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}}
|
||||
entry:
|
||||
store volatile i32 %i, i32* inttoptr (i32 786432 to i32*), align 262144
|
||||
ret i32 %i
|
||||
}
|
||||
|
||||
define i32* @f2(i32* nocapture %i) nounwind {
|
||||
entry:
|
||||
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##786432)
|
||||
%0 = load volatile i32* inttoptr (i32 786432 to i32*), align 262144
|
||||
%1 = inttoptr i32 %0 to i32*
|
||||
ret i32* %1
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user