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[PPC64] Fix SUBFC8 Defs list
Fix PR27943 "Bad machine code: Using an undefined physical register". SUBFC8 implicitly defines the CR0 register, but this was omitted in the instruction definition. Patch by Jameson Nash <jameson@juliacomputing.com> Reviewers: hfinkel Differential Revision: http://reviews.llvm.org/D20802 llvm-svn: 271425
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Keno Fischer
parent
02cf700a44
commit
2092f44163
@ -514,11 +514,11 @@ let Defs = [CARRY] in {
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def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
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"subfic $rD, $rA, $imm", IIC_IntGeneral,
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[(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
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defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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}
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defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"subfc", "$rT, $rA, $rB", IIC_IntGeneral,
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[(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
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PPC970_DGroup_Cracked;
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}
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defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"subf", "$rT, $rA, $rB", IIC_IntGeneral,
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[(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
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@ -1795,6 +1795,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
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MI->addOperand(*MI->getParent()->getParent(),
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MachineOperand::CreateReg(*ImpUses, false, true));
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}
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assert(MI->definesRegister(PPC::CR0) &&
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"Record-form instruction does not define cr0?");
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// Modify the condition code of operands in OperandsToUpdate.
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// Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
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143
test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
Normal file
143
test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
Normal file
@ -0,0 +1,143 @@
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# RUN: llc -start-after=machine-sink -stop-after=peephole-opts -mtriple=powerpc64-unknown-linux-gnu -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone
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declare i128 @llvm.cttz.i128(i128, i1) #0
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define void @fn1(i128, i128, i1) {
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top:
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br label %loop
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loop: ; preds = %loop, %top
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%v = phi i128 [ %3, %loop ], [ %0, %top ]
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%u = phi i128 [ %3, %loop ], [ %1, %top ]
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%s = sub i128 %v, %u
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%3 = call i128 @llvm.cttz.i128(i128 %s, i1 false)
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br label %loop
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}
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #1
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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...
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---
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name: fn1
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alignment: 2
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exposesReturnsTwice: false
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hasInlineAsm: false
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allVRegsAllocated: false
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isSSA: true
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tracksRegLiveness: true
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tracksSubRegLiveness: false
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registers:
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- { id: 0, class: g8rc }
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- { id: 1, class: g8rc }
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- { id: 2, class: g8rc }
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- { id: 3, class: g8rc }
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- { id: 4, class: g8rc }
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- { id: 5, class: g8rc }
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- { id: 6, class: g8rc }
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- { id: 7, class: g8rc }
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- { id: 8, class: g8rc }
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- { id: 9, class: g8rc }
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- { id: 10, class: g8rc }
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- { id: 11, class: g8rc }
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- { id: 12, class: g8rc }
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- { id: 13, class: g8rc }
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- { id: 14, class: g8rc }
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- { id: 15, class: g8rc_and_g8rc_nox0 }
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- { id: 16, class: g8rc_and_g8rc_nox0 }
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- { id: 17, class: g8rc }
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- { id: 18, class: g8rc }
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- { id: 19, class: g8rc }
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- { id: 20, class: g8rc }
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- { id: 21, class: g8rc }
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- { id: 22, class: g8rc }
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- { id: 23, class: g8rc }
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- { id: 24, class: g8rc }
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- { id: 25, class: crrc }
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- { id: 26, class: g8rc_and_g8rc_nox0 }
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- { id: 27, class: g8rc_and_g8rc_nox0 }
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liveins:
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- { reg: '%x3', virtual-reg: '%6' }
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- { reg: '%x4', virtual-reg: '%7' }
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- { reg: '%x5', virtual-reg: '%8' }
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- { reg: '%x6', virtual-reg: '%9' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0.top:
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successors: %bb.1.loop
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liveins: %x3, %x4, %x5, %x6
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%9 = COPY %x6
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%8 = COPY %x5
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%7 = COPY %x4
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%6 = COPY %x3
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%14 = COPY %9
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%13 = COPY %8
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%12 = COPY %7
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%11 = COPY %6
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%21 = LI8 128
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%23 = LI8 64
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bb.1.loop:
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successors: %bb.2.loop, %bb.4
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%0 = PHI %11, %bb.0.top, %4, %bb.3.loop
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%1 = PHI %12, %bb.0.top, %5, %bb.3.loop
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%2 = PHI %13, %bb.0.top, %4, %bb.3.loop
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%3 = PHI %14, %bb.0.top, %5, %bb.3.loop
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%15 = SUBFC8 %3, %1, implicit-def %carry
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%16 = SUBFE8 %2, %0, implicit-def dead %carry, implicit %carry
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%17 = ADDI8 %16, -1
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%18 = ADDI8 %15, -1
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%19 = ANDC8 killed %17, %16
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%20 = ANDC8 killed %18, %15
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%22 = CNTLZD killed %19
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%24 = CNTLZD killed %20
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%25 = CMPLDI %15, 0
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BCC 76, %25, %bb.2.loop
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; CHECK: SUBFC8o %3, %1, implicit-def %carry, implicit-def %cr0
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; CHECK: COPY killed %cr0
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; CHECK: BCC
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bb.4:
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successors: %bb.3.loop
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%27 = SUBF8 %24, %23
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B %bb.3.loop
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bb.2.loop:
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successors: %bb.3.loop
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%26 = SUBF8 %22, %21
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bb.3.loop:
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successors: %bb.1.loop
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%5 = PHI %26, %bb.2.loop, %27, %bb.4
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%4 = LI8 0
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B %bb.1.loop
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...
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