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more flags set right

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llvm-svn: 45860
This commit is contained in:
Chris Lattner 2008-01-11 07:18:17 +00:00
parent cb62477ec2
commit 20d1e419b3
3 changed files with 24 additions and 15 deletions
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1
lib/Target/X86/X86Instr64bit.td
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@ -526,6 +526,7 @@ let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
"shl{q}\t{$src2, $dst|$dst, $src2}", "shl{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>; [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
let neverHasSideEffects = 1 in
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
"shl{q}\t$dst", []>; "shl{q}\t$dst", []>;
} // isTwoAddress } // isTwoAddress

28
lib/Target/X86/X86InstrFPStack.td
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@ -166,6 +166,7 @@ class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
// Register copies. Just copies, the shortening ones do not truncate. // Register copies. Just copies, the shortening ones do not truncate.
let neverHasSideEffects = 1 in {
def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>; def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>; def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>; def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
@ -175,6 +176,7 @@ def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []
def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>; def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>; def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
def MOV_Fp8080 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>; def MOV_Fp8080 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
}
// Factoring for arithmetic. // Factoring for arithmetic.
multiclass FPBinary_rr<SDNode OpNode> { multiclass FPBinary_rr<SDNode OpNode> {
@ -293,12 +295,11 @@ defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
defm SIN : FPUnary<fsin, 0xFE, "fsin">; defm SIN : FPUnary<fsin, 0xFE, "fsin">;
defm COS : FPUnary<fcos, 0xFF, "fcos">; defm COS : FPUnary<fcos, 0xFF, "fcos">;
def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, let neverHasSideEffects = 1 in {
[]>; def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
[]>; def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, }
[]>;
def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9; def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
// Floating point cmovs. // Floating point cmovs.
@ -392,7 +393,7 @@ def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
[(truncstoref64 RFP80:$src, addr:$op)]>; [(truncstoref64 RFP80:$src, addr:$op)]>;
// FST does not support 80-bit memory target; FSTP must be used. // FST does not support 80-bit memory target; FSTP must be used.
let mayStore = 1 in { let mayStore = 1, neverHasSideEffects = 1 in {
def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
@ -401,7 +402,7 @@ def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
} }
def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
[(store RFP80:$src, addr:$op)]>; [(store RFP80:$src, addr:$op)]>;
let mayStore = 1 in { let mayStore = 1, neverHasSideEffects = 1 in {
def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
@ -498,17 +499,18 @@ def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
// Floating point compares. // Floating point compares.
let Defs = [EFLAGS] in { let Defs = [EFLAGS] in {
def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
[]>; // FPSW = cmp ST(0) with ST(i) []>; // FPSW = cmp ST(0) with ST(i)
def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
[]>; // FPSW = cmp ST(0) with ST(i)
def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
[]>; // FPSW = cmp ST(0) with ST(i)
def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
[(X86cmp RFP32:$lhs, RFP32:$rhs), [(X86cmp RFP32:$lhs, RFP32:$rhs),
(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
[]>; // FPSW = cmp ST(0) with ST(i)
def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
[(X86cmp RFP64:$lhs, RFP64:$rhs), [(X86cmp RFP64:$lhs, RFP64:$rhs),
(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
def UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
[]>; // FPSW = cmp ST(0) with ST(i)
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
[(X86cmp RFP80:$lhs, RFP80:$rhs), [(X86cmp RFP80:$lhs, RFP80:$rhs),
(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)

10
lib/Target/X86/X86InstrInfo.td
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@ -419,6 +419,7 @@ let isTwoAddress = 1 in // GR32 = bswap GR32
[(set GR32:$dst, (bswap GR32:$src))]>, TB; [(set GR32:$dst, (bswap GR32:$src))]>, TB;
// FIXME: Model xchg* as two address instructions? // FIXME: Model xchg* as two address instructions?
let neverHasSideEffects = 1 in {
def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
(outs), (ins GR8:$src1, GR8:$src2), (outs), (ins GR8:$src1, GR8:$src2),
"xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>; "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
@ -428,7 +429,9 @@ def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
(outs), (ins GR32:$src1, GR32:$src2), (outs), (ins GR32:$src1, GR32:$src2),
"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>; "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
}
let mayLoad = 1, mayStore = 1 in {
def XCHG8mr : I<0x86, MRMDestMem, def XCHG8mr : I<0x86, MRMDestMem,
(outs), (ins i8mem:$src1, GR8:$src2), (outs), (ins i8mem:$src1, GR8:$src2),
"xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>; "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
@ -447,6 +450,7 @@ def XCHG16rm : I<0x87, MRMSrcMem,
def XCHG32rm : I<0x87, MRMSrcMem, def XCHG32rm : I<0x87, MRMSrcMem,
(outs), (ins GR32:$src1, i32mem:$src2), (outs), (ins GR32:$src1, i32mem:$src2),
"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>; "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
}
// Bit scan instructions. // Bit scan instructions.
let Defs = [EFLAGS] in { let Defs = [EFLAGS] in {
@ -621,10 +625,10 @@ def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
// This probably ought to be moved to a def : Pat<> if the // This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted. // syntax can be accepted.
[(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
let Defs = [AX,DX,EFLAGS], Uses = [AX] in let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>, def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
OpSize; // AX,DX = AX*GR16 OpSize; // AX,DX = AX*GR16
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>; def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
// EAX,EDX = EAX*GR32 // EAX,EDX = EAX*GR32
let Defs = [AL,AH,EFLAGS], Uses = [AL] in let Defs = [AL,AH,EFLAGS], Uses = [AL] in
@ -1416,12 +1420,14 @@ def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
} }
// Shift left by one. Not used because (add x, x) is slightly cheaper. // Shift left by one. Not used because (add x, x) is slightly cheaper.
let neverHasSideEffects = 1 in {
def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
"shl{b}\t$dst", []>; "shl{b}\t$dst", []>;
def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
"shl{w}\t$dst", []>, OpSize; "shl{w}\t$dst", []>, OpSize;
def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
"shl{l}\t$dst", []>; "shl{l}\t$dst", []>;
}
let isTwoAddress = 0 in { let isTwoAddress = 0 in {
let Uses = [CL] in { let Uses = [CL] in {