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[RISCV] Define vector widening reduction intrinsic.
Define vwredsumu/vwredsum/vfwredosum/vfwredsum We work with @rogfer01 from BSC to come out this patch. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Differential Revision: https://reviews.llvm.org/D93807
This commit is contained in:
Monk Chiang
parent
5dfa98f2df
commit
20dc5d0c2f
@ -663,11 +663,17 @@ let TargetPrefix = "riscv" in {
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defm vredmaxu : RISCVReduction;
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defm vredmax : RISCVReduction;
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defm vwredsumu : RISCVReduction;
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defm vwredsum : RISCVReduction;
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defm vfredosum : RISCVReduction;
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defm vfredsum : RISCVReduction;
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defm vfredmin : RISCVReduction;
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defm vfredmax : RISCVReduction;
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defm vfwredsum : RISCVReduction;
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defm vfwredosum : RISCVReduction;
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def int_riscv_vmand: RISCVBinaryAAANoMask;
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def int_riscv_vmnand: RISCVBinaryAAANoMask;
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def int_riscv_vmandnot: RISCVBinaryAAANoMask;
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@ -1799,6 +1799,22 @@ multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat =
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}
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}
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multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat = 0> {
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foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in
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{
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defvar wtiSEW = !mul(vti.SEW, 2);
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if !le(wtiSEW, 64) then {
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defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1");
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defm : VPatTernary<intrinsic, instruction, "VS",
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wtiM1.Vector, vti.Vector,
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wtiM1.Vector, vti.Mask,
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vti.SEW, vti.LMul,
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wtiM1.RegClass, vti.RegClass,
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wtiM1.RegClass>;
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instructions and patterns.
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//===----------------------------------------------------------------------===//
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@ -2138,6 +2154,12 @@ defm PseudoVREDMINU : VPseudoReductionV_VS;
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defm PseudoVREDMIN : VPseudoReductionV_VS;
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defm PseudoVREDMAXU : VPseudoReductionV_VS;
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defm PseudoVREDMAX : VPseudoReductionV_VS;
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//===----------------------------------------------------------------------===//
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// 15.2. Vector Widening Integer Reduction Instructions
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//===----------------------------------------------------------------------===//
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defm PseudoVWREDSUMU : VPseudoReductionV_VS;
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defm PseudoVWREDSUM : VPseudoReductionV_VS;
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} // Predicates = [HasStdExtV]
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let Predicates = [HasStdExtV, HasStdExtF] in {
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@ -2148,6 +2170,12 @@ defm PseudoVFREDOSUM : VPseudoReductionV_VS;
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defm PseudoVFREDSUM : VPseudoReductionV_VS;
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defm PseudoVFREDMIN : VPseudoReductionV_VS;
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defm PseudoVFREDMAX : VPseudoReductionV_VS;
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//===----------------------------------------------------------------------===//
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// 15.4. Vector Widening Floating-Point Reduction Instructions
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//===----------------------------------------------------------------------===//
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defm PseudoVFWREDSUM : VPseudoReductionV_VS;
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defm PseudoVFWREDOSUM : VPseudoReductionV_VS;
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} // Predicates = [HasStdExtV, HasStdExtF]
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//===----------------------------------------------------------------------===//
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@ -2630,6 +2658,12 @@ defm "" : VPatReductionV_VS<"int_riscv_vredminu", "PseudoVREDMINU">;
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defm "" : VPatReductionV_VS<"int_riscv_vredmin", "PseudoVREDMIN">;
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defm "" : VPatReductionV_VS<"int_riscv_vredmaxu", "PseudoVREDMAXU">;
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defm "" : VPatReductionV_VS<"int_riscv_vredmax", "PseudoVREDMAX">;
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//===----------------------------------------------------------------------===//
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// 15.2. Vector Widening Integer Reduction Instructions
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//===----------------------------------------------------------------------===//
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defm "" : VPatReductionW_VS<"int_riscv_vwredsumu", "PseudoVWREDSUMU">;
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defm "" : VPatReductionW_VS<"int_riscv_vwredsum", "PseudoVWREDSUM">;
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} // Predicates = [HasStdExtV]
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let Predicates = [HasStdExtV, HasStdExtF] in {
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@ -2640,6 +2674,12 @@ defm "" : VPatReductionV_VS<"int_riscv_vfredosum", "PseudoVFREDOSUM", /*IsFloat=
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defm "" : VPatReductionV_VS<"int_riscv_vfredsum", "PseudoVFREDSUM", /*IsFloat=*/1>;
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defm "" : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", /*IsFloat=*/1>;
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defm "" : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", /*IsFloat=*/1>;
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//===----------------------------------------------------------------------===//
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// 15.4. Vector Widening Floating-Point Reduction Instructions
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//===----------------------------------------------------------------------===//
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defm "" : VPatReductionW_VS<"int_riscv_vfwredsum", "PseudoVFWREDSUM", /*IsFloat=*/1>;
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defm "" : VPatReductionW_VS<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", /*IsFloat=*/1>;
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} // Predicates = [HasStdExtV, HasStdExtF]
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//===----------------------------------------------------------------------===//
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43
test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll
Normal file
43
test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll
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@ -0,0 +1,43 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
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<vscale x 2 x float>,
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<vscale x 32 x half>,
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<vscale x 2 x float>,
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i32);
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define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
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; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
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<vscale x 2 x float> %0,
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<vscale x 32 x half> %1,
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<vscale x 2 x float> %2,
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i32 %3)
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ret <vscale x 2 x float> %a
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}
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declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.nxv32i1(
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<vscale x 2 x float>,
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<vscale x 32 x half>,
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<vscale x 2 x float>,
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<vscale x 32 x i1>,
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i32);
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define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
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; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.nxv32i1(
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<vscale x 2 x float> %0,
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<vscale x 32 x half> %1,
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<vscale x 2 x float> %2,
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<vscale x 32 x i1> %3,
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i32 %4)
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ret <vscale x 2 x float> %a
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}
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85
test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll
Normal file
85
test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll
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@ -0,0 +1,85 @@
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
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<vscale x 2 x float>,
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<vscale x 32 x half>,
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<vscale x 2 x float>,
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i64);
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define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
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; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
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<vscale x 2 x float> %0,
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<vscale x 32 x half> %1,
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<vscale x 2 x float> %2,
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i64 %3)
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ret <vscale x 2 x float> %a
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}
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declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.nxv32i1(
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<vscale x 2 x float>,
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<vscale x 32 x half>,
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<vscale x 2 x float>,
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<vscale x 32 x i1>,
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i64);
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define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
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; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.nxv32i1(
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<vscale x 2 x float> %0,
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<vscale x 32 x half> %1,
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<vscale x 2 x float> %2,
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<vscale x 32 x i1> %3,
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i64 %4)
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ret <vscale x 2 x float> %a
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}
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declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
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<vscale x 1 x double>,
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<vscale x 16 x float>,
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<vscale x 1 x double>,
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i64);
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define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
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; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
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<vscale x 1 x double> %0,
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<vscale x 16 x float> %1,
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<vscale x 1 x double> %2,
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i64 %3)
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ret <vscale x 1 x double> %a
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}
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declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv16i1(
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<vscale x 1 x double>,
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<vscale x 16 x float>,
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<vscale x 1 x double>,
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<vscale x 16 x i1>,
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i64);
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define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
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; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv16i1(
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<vscale x 1 x double> %0,
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<vscale x 16 x float> %1,
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<vscale x 1 x double> %2,
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<vscale x 16 x i1> %3,
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i64 %4)
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ret <vscale x 1 x double> %a
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}
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43
test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll
Normal file
43
test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll
Normal file
@ -0,0 +1,43 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
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<vscale x 2 x float>,
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<vscale x 32 x half>,
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<vscale x 2 x float>,
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i32);
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define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
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; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
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<vscale x 2 x float> %0,
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<vscale x 32 x half> %1,
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<vscale x 2 x float> %2,
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i32 %3)
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ret <vscale x 2 x float> %a
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}
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declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16.nxv32i1(
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<vscale x 2 x float>,
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<vscale x 32 x half>,
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<vscale x 2 x float>,
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<vscale x 32 x i1>,
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i32);
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define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
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; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16.nxv32i1(
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<vscale x 2 x float> %0,
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<vscale x 32 x half> %1,
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<vscale x 2 x float> %2,
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<vscale x 32 x i1> %3,
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i32 %4)
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ret <vscale x 2 x float> %a
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}
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85
test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll
Normal file
85
test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll
Normal file
@ -0,0 +1,85 @@
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
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<vscale x 2 x float>,
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<vscale x 32 x half>,
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<vscale x 2 x float>,
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i64);
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define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
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; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
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<vscale x 2 x float> %0,
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<vscale x 32 x half> %1,
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<vscale x 2 x float> %2,
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i64 %3)
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ret <vscale x 2 x float> %a
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}
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declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16.nxv32i1(
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<vscale x 2 x float>,
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<vscale x 32 x half>,
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<vscale x 2 x float>,
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<vscale x 32 x i1>,
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i64);
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define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
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; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
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%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16.nxv32i1(
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<vscale x 2 x float> %0,
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<vscale x 32 x half> %1,
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<vscale x 2 x float> %2,
|
||||
<vscale x 32 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 1 x double>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
|
||||
entry:
|
||||
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64
|
||||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
|
||||
; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 16 x float> %1,
|
||||
<vscale x 1 x double> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv16i1(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 16 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
||||
entry:
|
||||
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64
|
||||
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
|
||||
; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv16i1(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 16 x float> %1,
|
||||
<vscale x 1 x double> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user