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Handle SUBREG_TO_REG instructions with the same heuristics
as INSERT_SUBREG instructions in the list-burr scheduler. llvm-svn: 69308
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@ -1019,9 +1019,10 @@ namespace {
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// avoid spilling.
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// avoid spilling.
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return 0;
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return 0;
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if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
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if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
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Opc == TargetInstrInfo::SUBREG_TO_REG ||
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Opc == TargetInstrInfo::INSERT_SUBREG)
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Opc == TargetInstrInfo::INSERT_SUBREG)
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// EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to
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// EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
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// facilitate coalescing.
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// close to their uses to facilitate coalescing.
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return 0;
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return 0;
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if (SU->NumSuccs == 0 && SU->NumPreds != 0)
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if (SU->NumSuccs == 0 && SU->NumPreds != 0)
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// If SU does not have a register use, i.e. it doesn't produce a value
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// If SU does not have a register use, i.e. it doesn't produce a value
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@ -1396,11 +1397,12 @@ void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
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if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
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if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
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continue;
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continue;
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}
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}
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// Don't constrain extract_subreg / insert_subreg; these may be
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// Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG;
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// coalesced away. We want them close to their uses.
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// these may be coalesced away. We want them close to their uses.
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unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
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unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
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if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
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if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
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SuccOpc == TargetInstrInfo::INSERT_SUBREG)
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SuccOpc == TargetInstrInfo::INSERT_SUBREG ||
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SuccOpc == TargetInstrInfo::SUBREG_TO_REG)
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continue;
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continue;
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if ((!canClobber(SuccSU, DUSU) ||
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if ((!canClobber(SuccSU, DUSU) ||
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(hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
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(hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
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