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https://github.com/RPCS3/llvm-mirror.git
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Bug fixes for not using unified reg. numbers, and for using the
wrong register class for saving CC registers. Also, use distinct names for the three types of SetMachineOperand. llvm-svn: 1895
This commit is contained in:
Vikram S. Adve
parent
778410c47a
commit
217f7b1fe1
@ -32,16 +32,20 @@ UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
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}
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// getZeroRegNum - returns the register that contains always zero this is the
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// unified register number
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// getZeroRegNum - returns the register that contains always zero.
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// this is the unified register number
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//
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int UltraSparcRegInfo::getZeroRegNum() const { return SparcIntRegOrder::g0; }
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int UltraSparcRegInfo::getZeroRegNum() const {
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return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegOrder::g0);
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}
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// getCallAddressReg - returns the reg used for pushing the address when a
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// method is called. This can be used for other purposes between calls
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//
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unsigned UltraSparcRegInfo::getCallAddressReg() const {
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return SparcIntRegOrder::o7;
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return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegOrder::o7);
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}
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// Returns the register containing the return address.
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@ -49,7 +53,8 @@ unsigned UltraSparcRegInfo::getCallAddressReg() const {
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// value when a return instruction is reached.
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//
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unsigned UltraSparcRegInfo::getReturnAddressReg() const {
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return SparcIntRegOrder::i7;
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return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegOrder::i7);
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}
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// given the unified register number, this gives the name
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@ -71,12 +76,16 @@ const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
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return "";
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}
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// Get unified reg number for frame pointer
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unsigned UltraSparcRegInfo::getFramePointer() const {
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return SparcIntRegOrder::i6;
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return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegOrder::i6);
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}
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// Get unified reg number for stack pointer
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unsigned UltraSparcRegInfo::getStackPointer() const {
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return SparcIntRegOrder::o6;
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return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegOrder::o6);
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}
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@ -1037,21 +1046,21 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
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case IntCCRegType:
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case FloatCCRegType:
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MI = new MachineInstr(ADD, 3);
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MI->SetMachineOperand(0, SrcReg, false);
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MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
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MI->SetMachineOperand(2, DestReg, true);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
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MI->SetMachineOperandReg(2, DestReg, true);
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break;
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case FPSingleRegType:
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MI = new MachineInstr(FMOVS, 2);
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MI->SetMachineOperand(0, SrcReg, false);
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MI->SetMachineOperand(1, DestReg, true);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, DestReg, true);
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break;
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case FPDoubleRegType:
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MI = new MachineInstr(FMOVD, 2);
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MI->SetMachineOperand(0, SrcReg, false);
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MI->SetMachineOperand(1, DestReg, true);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, DestReg, true);
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break;
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default:
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@ -1076,26 +1085,26 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
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case IntRegType:
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case FloatCCRegType:
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MI = new MachineInstr(STX, 3);
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MI->SetMachineOperand(0, SrcReg, false);
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MI->SetMachineOperand(1, DestPtrReg, false);
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MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset, false);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, DestPtrReg, false);
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MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset);
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break;
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case FPSingleRegType:
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MI = new MachineInstr(ST, 3);
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MI->SetMachineOperand(0, SrcReg, false);
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MI->SetMachineOperand(1, DestPtrReg, false);
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MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset, false);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, DestPtrReg, false);
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MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset);
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break;
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case FPDoubleRegType:
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MI = new MachineInstr(STD, 3);
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MI->SetMachineOperand(0, SrcReg, false);
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MI->SetMachineOperand(1, DestPtrReg, false);
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MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset, false);
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MI->SetMachineOperandReg(0, SrcReg, false);
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MI->SetMachineOperandReg(1, DestPtrReg, false);
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MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset);
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break;
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case IntCCRegType:
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@ -1124,27 +1133,27 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
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case IntRegType:
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case FloatCCRegType:
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MI = new MachineInstr(LDX, 3);
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MI->SetMachineOperand(0, SrcPtrReg, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset, false);
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MI->SetMachineOperand(2, DestReg, true);
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MI->SetMachineOperandReg(0, SrcPtrReg, false);
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MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset);
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MI->SetMachineOperandReg(2, DestReg, true);
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break;
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case FPSingleRegType:
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MI = new MachineInstr(LD, 3);
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MI->SetMachineOperand(0, SrcPtrReg, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset, false);
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MI->SetMachineOperand(2, DestReg, true);
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MI->SetMachineOperandReg(0, SrcPtrReg, false);
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MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset);
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MI->SetMachineOperandReg(2, DestReg, true);
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break;
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case FPDoubleRegType:
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MI = new MachineInstr(LDD, 3);
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MI->SetMachineOperand(0, SrcPtrReg, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset, false);
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MI->SetMachineOperand(2, DestReg, true);
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MI->SetMachineOperandReg(0, SrcPtrReg, false);
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MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset);
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MI->SetMachineOperandReg(2, DestReg, true);
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break;
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case IntCCRegType:
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@ -1177,22 +1186,22 @@ MachineInstr *UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const {
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switch( RegType ) {
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case IntRegType:
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MI = new MachineInstr(ADD, 3);
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MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
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MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true);
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MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
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MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
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break;
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case FPSingleRegType:
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MI = new MachineInstr(FMOVS, 2);
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MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
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MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
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break;
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case FPDoubleRegType:
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MI = new MachineInstr(FMOVD, 2);
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MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
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MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
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MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
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break;
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default:
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@ -1291,9 +1300,8 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
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getSpilledRegSize(RegType));
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MachineInstr *AdIBefCC, *AdIAftCC, *AdICpCC;
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MachineInstr *AdIBef, *AdIAft;
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MachineInstr *AdIBefCC=NULL, *AdIAftCC=NULL, *AdICpCC;
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MachineInstr *AdIBef=NULL, *AdIAft=NULL;
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//---- Insert code for pushing the reg on stack ----------
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@ -1307,9 +1315,9 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
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// get a free INTEGER register
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int FreeIntReg =
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PRA.getUsableUniRegAtMI(LR->getRegClass(), IntRegType, MInst,
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&LVSetBef, AdIBefCC, AdIAftCC);
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PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /*LR->getRegClass()*/,
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IntRegType, MInst, &LVSetBef, AdIBefCC, AdIAftCC);
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// insert the instructions in reverse order since we are
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// adding them to the front of InstrnsBefore
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@ -1345,8 +1353,8 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
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// get a free INT register
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int FreeIntReg =
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PRA.getUsableUniRegAtMI(LR->getRegClass(), IntRegType, MInst,
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&LVSetAft, AdIBefCC, AdIAftCC);
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PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /* LR->getRegClass()*/,
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IntRegType, MInst, &LVSetAft, AdIBefCC, AdIAftCC);
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if(AdIBefCC)
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PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIBefCC);
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@ -1376,10 +1384,14 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
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if(DEBUG_RA) {
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cerr << "\nFor call inst:" << *MInst;
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cerr << " -inserted caller saving instrs:\n\t ";
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if( RegType == IntCCRegType )
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cerr << *AdIBefCC << "\t" << *AdIAftCC ;
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else
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cerr << *AdIBef << "\t" << *AdIAft ;
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if( RegType == IntCCRegType ) {
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if(AdIBefCC) cerr << *AdIBefCC << "\t";
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if(AdIAftCC) cerr << *AdIAftCC;
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}
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else {
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if(AdIBef) cerr << *AdIBef << "\t";
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if(AdIAft) cerr << *AdIAft;
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}
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}
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} // if not already pushed
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@ -1400,8 +1412,10 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
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MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
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MachineInstr * MI = new MachineInstr(RDCCR, 2);
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MI->SetMachineOperand(0, SparcIntCCRegOrder::ccr, false);
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MI->SetMachineOperand(1, IntReg, true);
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MI->SetMachineOperandReg(0, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
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SparcIntCCRegOrder::ccr),
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false, true);
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MI->SetMachineOperandReg(1, IntReg, true);
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return MI;
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}
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@ -1412,9 +1426,10 @@ MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
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MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
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MachineInstr *MI = new MachineInstr(WRCCR, 3);
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MI->SetMachineOperand(0, IntReg, false);
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MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
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MI->SetMachineOperand(2, SparcIntCCRegOrder::ccr, true);
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MI->SetMachineOperandReg(0, IntReg, false);
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MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
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MI->SetMachineOperandReg(2, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, SparcIntCCRegOrder::ccr),
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true, true);
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return MI;
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}
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