From 219b65e574c14a6ef533aa5284d32f8aae7b137f Mon Sep 17 00:00:00 2001
From: David Green <david.green@arm.com>
Date: Thu, 21 Jun 2018 15:48:29 +0000
Subject: [PATCH] [ARM] Enable useAA() for the in-order Cortex-R52

This option allows codegen (such as DAGCombine or MI scheduling) to use alias
analysis information, which can help with the codegen on in-order cpu's,
especially machine scheduling. Here I have done things the same way as AArch64,
adding a subtarget feature to enable this for specific cores, and enabled it for
the R52 where we have a schedule to make use of it.

Differential Revision: https://reviews.llvm.org/D48074

llvm-svn: 335249
---
 lib/Target/ARM/ARM.td         |  7 ++++++-
 lib/Target/ARM/ARMSubtarget.h |  7 +++++++
 test/CodeGen/ARM/useaa.ll     | 26 ++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/ARM/useaa.ll

diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 2c3587e6d1a..7b551c40408 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -330,6 +330,10 @@ def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
     "DisablePostRAScheduler", "true",
     "Don't schedule again after register allocation">;
 
+// Enable use of alias analysis during code generation
+def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
+                                    "Use alias analysis during codegen">;
+
 //===----------------------------------------------------------------------===//
 // ARM architecture class
 //
@@ -1006,7 +1010,8 @@ def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
 
 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
                                                          FeatureUseMISched,
-                                                         FeatureFPAO]>;
+                                                         FeatureFPAO,
+                                                         FeatureUseAA]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index e23a5fe1e06..f72b97fc0d7 100644
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -198,6 +198,9 @@ protected:
   /// register allocation.
   bool DisablePostRAScheduler = false;
 
+  /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
+  bool UseAA = false;
+
   /// HasThumb2 - True if Thumb2 instructions are supported.
   bool HasThumb2 = false;
 
@@ -723,6 +726,10 @@ public:
   /// True for some subtargets at > -O0.
   bool enablePostRAScheduler() const override;
 
+  /// Enable use of alias analysis during code generation (during MI
+  /// scheduling, DAGCombine, etc.).
+  bool useAA() const override { return UseAA; }
+
   // enableAtomicExpand- True if we need to expand our atomics.
   bool enableAtomicExpand() const override;
 
diff --git a/test/CodeGen/ARM/useaa.ll b/test/CodeGen/ARM/useaa.ll
new file mode 100644
index 00000000000..d7913e7bad9
--- /dev/null
+++ b/test/CodeGen/ARM/useaa.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
+
+; Check we use AA during codegen, so can interleave these loads/stores.
+
+; CHECK-LABEL: test
+; GENERIC: ldr
+; GENERIC: str
+; GENERIC: ldr
+; GENERIC: str
+; USEAA: ldr
+; USEAA: ldr
+; USEAA: str
+; USEAA: str
+
+define void @test(i32* nocapture %a, i32* noalias nocapture %b) {
+entry:
+  %0 = load i32, i32* %a, align 4
+  %add = add nsw i32 %0, 10
+  store i32 %add, i32* %a, align 4
+  %1 = load i32, i32* %b, align 4
+  %add2 = add nsw i32 %1, 20
+  store i32 %add2, i32* %b, align 4
+  ret void
+}
+