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ARM: allow rewriting frame indexes for all prefetch variants.

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For some reason we could handle PLD but not PLDW or PLI, but all of them can
potentially refer to the stack region (if weirdly for PLI).
This commit is contained in:
Tim Northover 2019-11-14 13:26:53 +00:00
parent 96432067a7
commit 21acb96c61
2 changed files with 63 additions and 0 deletions
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14
lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -375,6 +375,8 @@ negativeOffsetOpcode(unsigned opcode)
case ARM::t2STRBi12: return ARM::t2STRBi8; case ARM::t2STRBi12: return ARM::t2STRBi8;
case ARM::t2STRHi12: return ARM::t2STRHi8; case ARM::t2STRHi12: return ARM::t2STRHi8;
case ARM::t2PLDi12: return ARM::t2PLDi8; case ARM::t2PLDi12: return ARM::t2PLDi8;
case ARM::t2PLDWi12: return ARM::t2PLDWi8;
case ARM::t2PLIi12: return ARM::t2PLIi8;
case ARM::t2LDRi8: case ARM::t2LDRi8:
case ARM::t2LDRHi8: case ARM::t2LDRHi8:
@ -385,6 +387,8 @@ negativeOffsetOpcode(unsigned opcode)
case ARM::t2STRBi8: case ARM::t2STRBi8:
case ARM::t2STRHi8: case ARM::t2STRHi8:
case ARM::t2PLDi8: case ARM::t2PLDi8:
case ARM::t2PLDWi8:
case ARM::t2PLIi8:
return opcode; return opcode;
default: default:
@ -405,6 +409,8 @@ positiveOffsetOpcode(unsigned opcode)
case ARM::t2STRBi8: return ARM::t2STRBi12; case ARM::t2STRBi8: return ARM::t2STRBi12;
case ARM::t2STRHi8: return ARM::t2STRHi12; case ARM::t2STRHi8: return ARM::t2STRHi12;
case ARM::t2PLDi8: return ARM::t2PLDi12; case ARM::t2PLDi8: return ARM::t2PLDi12;
case ARM::t2PLDWi8: return ARM::t2PLDWi12;
case ARM::t2PLIi8: return ARM::t2PLIi12;
case ARM::t2LDRi12: case ARM::t2LDRi12:
case ARM::t2LDRHi12: case ARM::t2LDRHi12:
@ -415,6 +421,8 @@ positiveOffsetOpcode(unsigned opcode)
case ARM::t2STRBi12: case ARM::t2STRBi12:
case ARM::t2STRHi12: case ARM::t2STRHi12:
case ARM::t2PLDi12: case ARM::t2PLDi12:
case ARM::t2PLDWi12:
case ARM::t2PLIi12:
return opcode; return opcode;
default: default:
@ -435,6 +443,8 @@ immediateOffsetOpcode(unsigned opcode)
case ARM::t2STRBs: return ARM::t2STRBi12; case ARM::t2STRBs: return ARM::t2STRBi12;
case ARM::t2STRHs: return ARM::t2STRHi12; case ARM::t2STRHs: return ARM::t2STRHi12;
case ARM::t2PLDs: return ARM::t2PLDi12; case ARM::t2PLDs: return ARM::t2PLDi12;
case ARM::t2PLDWs: return ARM::t2PLDWi12;
case ARM::t2PLIs: return ARM::t2PLIi12;
case ARM::t2LDRi12: case ARM::t2LDRi12:
case ARM::t2LDRHi12: case ARM::t2LDRHi12:
@ -445,6 +455,8 @@ immediateOffsetOpcode(unsigned opcode)
case ARM::t2STRBi12: case ARM::t2STRBi12:
case ARM::t2STRHi12: case ARM::t2STRHi12:
case ARM::t2PLDi12: case ARM::t2PLDi12:
case ARM::t2PLDWi12:
case ARM::t2PLIi12:
case ARM::t2LDRi8: case ARM::t2LDRi8:
case ARM::t2LDRHi8: case ARM::t2LDRHi8:
case ARM::t2LDRBi8: case ARM::t2LDRBi8:
@ -454,6 +466,8 @@ immediateOffsetOpcode(unsigned opcode)
case ARM::t2STRBi8: case ARM::t2STRBi8:
case ARM::t2STRHi8: case ARM::t2STRHi8:
case ARM::t2PLDi8: case ARM::t2PLDi8:
case ARM::t2PLDWi8:
case ARM::t2PLIi8:
return opcode; return opcode;
default: default:

49
test/CodeGen/ARM/prefetch.ll
View File

@ -1,5 +1,6 @@
; RUN: llc -mtriple=thumb-eabi -mattr=-thumb2 %s -o - | FileCheck %s -check-prefix CHECK-T1 ; RUN: llc -mtriple=thumb-eabi -mattr=-thumb2 %s -o - | FileCheck %s -check-prefix CHECK-T1
; RUN: llc -mtriple=thumb-eabi -mattr=+v7 %s -o - | FileCheck %s -check-prefix=THUMB2 ; RUN: llc -mtriple=thumb-eabi -mattr=+v7 %s -o - | FileCheck %s -check-prefix=THUMB2
; RUN: llc -mtriple=thumb-eabi -mattr=+v7 -mattr=+mp %s -o - | FileCheck %s -check-prefix=THUMB2-MP
; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s -check-prefix=ARM ; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s -check-prefix=ARM
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=ARM-MP ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=ARM-MP
; rdar://8601536 ; rdar://8601536
@ -83,15 +84,63 @@ entry:
;ARM-LABEL: t6: ;ARM-LABEL: t6:
;ARM: pld [sp] ;ARM: pld [sp]
;ARM: pld [sp, #50] ;ARM: pld [sp, #50]
;ARM: pld [sp, #-50]
;THUMB2-LABEL: t6: ;THUMB2-LABEL: t6:
;THUMB2: pld [sp] ;THUMB2: pld [sp]
;THUMB2: pld [sp, #50] ;THUMB2: pld [sp, #50]
;THUMB2: pld [sp, #-50]
%red = alloca [100 x i8], align 1 %red = alloca [100 x i8], align 1
%0 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 0 %0 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 0
%1 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 50 %1 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 50
%2 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 -50
call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1) call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1)
call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1) call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
call void @llvm.prefetch(i8* %2, i32 0, i32 3, i32 1)
ret void
}
define void @t7() {
entry:
;ARM-LABEL: t7:
;ARM-MP: pldw [sp]
;ARM-MP: pldw [sp, #50]
;ARM-MP: pldw [sp, #-50]
;THUMB2-MP-LABEL: t7:
;THUMB2-MP: pldw [sp]
;THUMB2-MP: pldw [sp, #50]
;THUMB2-MP: pldw [sp, #-50]
%red = alloca [100 x i8], align 1
%0 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 0
%1 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 50
%2 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 -50
call void @llvm.prefetch(i8* %0, i32 1, i32 3, i32 1)
call void @llvm.prefetch(i8* %1, i32 1, i32 3, i32 1)
call void @llvm.prefetch(i8* %2, i32 1, i32 3, i32 1)
ret void
}
define void @t8() {
entry:
;ARM-LABEL: t8:
;ARM: pli [sp]
;ARM: pli [sp, #50]
;ARM: pli [sp, #-50]
;THUMB2-LABEL: t8:
;THUMB2: pli [sp]
;THUMB2: pli [sp, #50]
;THUMB2: pli [sp, #-50]
%red = alloca [100 x i8], align 1
%0 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 0
%1 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 50
%2 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 -50
call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 0)
call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 0)
call void @llvm.prefetch(i8* %2, i32 0, i32 3, i32 0)
ret void ret void
} }