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[RISCV] Ensure small mask BUILD_VECTORs aren't expanded
The default expansion for BUILD_VECTORs -- save for going through shuffles -- is to go through the stack. This method only works when the type is at least byte-sized, so for v2i1 and v4i1 we would crash. This patch ensures that small mask-type BUILD_VECTORs are always handled without crashing. We lower to a SETCC of the equivalent i8 type. This also exposes some pre-existing issues where the lowering when optimizing for size results in larger code than without. Those will be tackled in future patches. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D102767
This commit is contained in:
Fraser Cormack
parent
c18c30409c
commit
21ba453e3b
@ -1367,12 +1367,15 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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// according to the size of the final vector - use i8 chunks rather than
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// XLenVT if we're producing a v8i1. This results in more consistent
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// codegen across RV32 and RV64.
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// If we have to use more than one INSERT_VECTOR_ELT then this optimization
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// is likely to increase code size; avoid peforming it in such a case.
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unsigned NumViaIntegerBits =
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std::min(std::max(NumElts, 8u), Subtarget.getXLen());
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if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
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(!DAG.shouldOptForSize() || NumElts <= NumViaIntegerBits)) {
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if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
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// If we have to use more than one INSERT_VECTOR_ELT then this
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// optimization is likely to increase code size; avoid peforming it in
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// such a case. We can go through the stack as long as we're at least
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// byte-sized.
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if (DAG.shouldOptForSize() && NumElts > NumViaIntegerBits)
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return SDValue();
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// Now we can create our integer vector type. Note that it may be larger
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// than the resulting mask type: v4i1 would use v1i8 as its integer type.
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MVT IntegerViaVecVT =
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@ -1427,20 +1430,29 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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return Vec;
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}
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// A splat can be lowered as a SETCC. For each fixed-length mask vector
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// type, we have a legal equivalently-sized i8 type, so we can use that.
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// A BUILD_VECTOR can be lowered as a SETCC. For each fixed-length mask
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// vector type, we have a legal equivalently-sized i8 type, so we can use
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// that.
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MVT WideVecVT = VT.changeVectorElementType(MVT::i8);
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SDValue VecZero = DAG.getConstant(0, DL, WideVecVT);
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SDValue WideVec;
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if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue()) {
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// For a splat, perform a scalar truncate before creating the wider
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// vector.
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assert(Splat.getValueType() == XLenVT &&
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"Unexpected type for i1 splat value");
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MVT InterVT = VT.changeVectorElementType(MVT::i8);
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Splat = DAG.getNode(ISD::AND, DL, XLenVT, Splat,
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DAG.getConstant(1, DL, XLenVT));
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Splat = DAG.getSplatBuildVector(InterVT, DL, Splat);
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SDValue Zero = DAG.getConstant(0, DL, InterVT);
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return DAG.getSetCC(DL, VT, Splat, Zero, ISD::SETNE);
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WideVec = DAG.getSplatBuildVector(WideVecVT, DL, Splat);
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} else {
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SmallVector<SDValue, 8> Ops(Op->op_values());
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WideVec = DAG.getBuildVector(WideVecVT, DL, Ops);
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SDValue VecOne = DAG.getConstant(1, DL, WideVecVT);
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WideVec = DAG.getNode(ISD::AND, DL, WideVecVT, WideVec, VecOne);
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}
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return SDValue();
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return DAG.getSetCC(DL, VT, WideVec, VecZero, ISD::SETNE);
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}
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if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue()) {
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@ -8,6 +8,64 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX8
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX8
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define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) {
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; CHECK-LABEL: buildvec_mask_nonconst_v1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: vsetivli a1, 1, e8,mf8,ta,mu
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; CHECK-NEXT: vmv.v.x v25, a0
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: ret
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%1 = insertelement <1 x i1> undef, i1 %x, i32 0
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ret <1 x i1> %1
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}
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define <1 x i1> @buildvec_mask_optsize_nonconst_v1i1(i1 %x) optsize {
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; CHECK-LABEL: buildvec_mask_optsize_nonconst_v1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: vsetivli a1, 1, e8,mf8,ta,mu
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; CHECK-NEXT: vmv.v.x v25, a0
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: ret
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%1 = insertelement <1 x i1> undef, i1 %x, i32 0
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ret <1 x i1> %1
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}
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define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) {
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; CHECK-LABEL: buildvec_mask_nonconst_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a2, 2, e8,mf8,ta,mu
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; CHECK-NEXT: vmv.v.x v25, a1
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; CHECK-NEXT: vmv.s.x v25, a0
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; CHECK-NEXT: vand.vi v25, v25, 1
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: ret
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%1 = insertelement <2 x i1> undef, i1 %x, i32 0
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%2 = insertelement <2 x i1> %1, i1 %y, i32 1
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ret <2 x i1> %2
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}
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; FIXME: optsize isn't smaller than the code above
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define <2 x i1> @buildvec_mask_optsize_nonconst_v2i1(i1 %x, i1 %y) optsize {
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; CHECK-LABEL: buildvec_mask_optsize_nonconst_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: sb a1, 15(sp)
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; CHECK-NEXT: sb a0, 14(sp)
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; CHECK-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
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; CHECK-NEXT: addi a0, sp, 14
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; CHECK-NEXT: vle8.v v25, (a0)
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; CHECK-NEXT: vand.vi v25, v25, 1
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%1 = insertelement <2 x i1> undef, i1 %x, i32 0
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%2 = insertelement <2 x i1> %1, i1 %y, i32 1
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ret <2 x i1> %2
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}
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define <3 x i1> @buildvec_mask_v1i1() {
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; CHECK-LABEL: buildvec_mask_v1i1:
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; CHECK: # %bb.0:
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@ -38,6 +96,73 @@ define <4 x i1> @buildvec_mask_v4i1() {
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ret <4 x i1> <i1 0, i1 1, i1 1, i1 0>
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}
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define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {
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; CHECK-LABEL: buildvec_mask_nonconst_v4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a2, zero, 3
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; CHECK-NEXT: vsetivli a3, 1, e8,mf8,ta,mu
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; CHECK-NEXT: vmv.s.x v0, a2
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; CHECK-NEXT: vsetivli a2, 4, e8,mf4,ta,mu
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; CHECK-NEXT: vmv.v.x v25, a1
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; CHECK-NEXT: vmerge.vxm v25, v25, a0, v0
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; CHECK-NEXT: vand.vi v25, v25, 1
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: ret
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%1 = insertelement <4 x i1> undef, i1 %x, i32 0
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%2 = insertelement <4 x i1> %1, i1 %x, i32 1
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%3 = insertelement <4 x i1> %2, i1 %y, i32 2
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%4 = insertelement <4 x i1> %3, i1 %y, i32 3
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ret <4 x i1> %4
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}
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; FIXME: optsize isn't smaller than the code above
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define <4 x i1> @buildvec_mask_optsize_nonconst_v4i1(i1 %x, i1 %y) optsize {
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; CHECK-LABEL: buildvec_mask_optsize_nonconst_v4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: sb a1, 15(sp)
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; CHECK-NEXT: sb a1, 14(sp)
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; CHECK-NEXT: sb a0, 13(sp)
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; CHECK-NEXT: sb a0, 12(sp)
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; CHECK-NEXT: vsetivli a0, 4, e8,mf4,ta,mu
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; CHECK-NEXT: addi a0, sp, 12
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; CHECK-NEXT: vle8.v v25, (a0)
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; CHECK-NEXT: vand.vi v25, v25, 1
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%1 = insertelement <4 x i1> undef, i1 %x, i32 0
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%2 = insertelement <4 x i1> %1, i1 %x, i32 1
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%3 = insertelement <4 x i1> %2, i1 %y, i32 2
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%4 = insertelement <4 x i1> %3, i1 %y, i32 3
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ret <4 x i1> %4
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}
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define <4 x i1> @buildvec_mask_nonconst_v4i1_2(i1 %x, i1 %y) {
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; CHECK-LABEL: buildvec_mask_nonconst_v4i1_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: sb a1, 15(sp)
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; CHECK-NEXT: addi a1, zero, 1
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; CHECK-NEXT: sb a1, 14(sp)
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; CHECK-NEXT: sb a0, 13(sp)
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; CHECK-NEXT: sb zero, 12(sp)
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; CHECK-NEXT: vsetivli a0, 4, e8,mf4,ta,mu
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; CHECK-NEXT: addi a0, sp, 12
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; CHECK-NEXT: vle8.v v25, (a0)
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; CHECK-NEXT: vand.vi v25, v25, 1
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%1 = insertelement <4 x i1> undef, i1 0, i32 0
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%2 = insertelement <4 x i1> %1, i1 %x, i32 1
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%3 = insertelement <4 x i1> %2, i1 1, i32 2
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%4 = insertelement <4 x i1> %3, i1 %y, i32 3
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ret <4 x i1> %4
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}
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define <8 x i1> @buildvec_mask_v8i1() {
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; CHECK-LABEL: buildvec_mask_v8i1:
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; CHECK: # %bb.0:
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@ -48,6 +173,124 @@ define <8 x i1> @buildvec_mask_v8i1() {
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ret <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
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}
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define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) {
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; CHECK-LABEL: buildvec_mask_nonconst_v8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a2, zero, 19
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; CHECK-NEXT: vsetivli a3, 1, e8,mf8,ta,mu
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; CHECK-NEXT: vmv.s.x v0, a2
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; CHECK-NEXT: vsetivli a2, 8, e8,mf2,ta,mu
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; CHECK-NEXT: vmv.v.x v25, a1
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; CHECK-NEXT: vmerge.vxm v25, v25, a0, v0
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; CHECK-NEXT: vand.vi v25, v25, 1
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: ret
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%1 = insertelement <8 x i1> undef, i1 %x, i32 0
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%2 = insertelement <8 x i1> %1, i1 %x, i32 1
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%3 = insertelement <8 x i1> %2, i1 %y, i32 2
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%4 = insertelement <8 x i1> %3, i1 %y, i32 3
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%5 = insertelement <8 x i1> %4, i1 %x, i32 4
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%6 = insertelement <8 x i1> %5, i1 %y, i32 5
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%7 = insertelement <8 x i1> %6, i1 %y, i32 6
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%8 = insertelement <8 x i1> %7, i1 %y, i32 7
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ret <8 x i1> %8
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}
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define <8 x i1> @buildvec_mask_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) {
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; CHECK-LABEL: buildvec_mask_nonconst_v8i1_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: sb a2, 15(sp)
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; CHECK-NEXT: sb zero, 14(sp)
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; CHECK-NEXT: sb a3, 13(sp)
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; CHECK-NEXT: sb a0, 12(sp)
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; CHECK-NEXT: sb a1, 11(sp)
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; CHECK-NEXT: addi a1, zero, 1
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; CHECK-NEXT: sb a1, 10(sp)
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; CHECK-NEXT: sb a0, 9(sp)
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; CHECK-NEXT: sb a0, 8(sp)
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; CHECK-NEXT: vsetivli a0, 8, e8,mf2,ta,mu
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; CHECK-NEXT: addi a0, sp, 8
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; CHECK-NEXT: vle8.v v25, (a0)
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; CHECK-NEXT: vand.vi v25, v25, 1
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%1 = insertelement <8 x i1> undef, i1 %x, i32 0
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%2 = insertelement <8 x i1> %1, i1 %x, i32 1
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%3 = insertelement <8 x i1> %2, i1 1, i32 2
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%4 = insertelement <8 x i1> %3, i1 %y, i32 3
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%5 = insertelement <8 x i1> %4, i1 %x, i32 4
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%6 = insertelement <8 x i1> %5, i1 %w, i32 5
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%7 = insertelement <8 x i1> %6, i1 0, i32 6
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%8 = insertelement <8 x i1> %7, i1 %z, i32 7
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ret <8 x i1> %8
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}
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define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) optsize {
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; CHECK-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: sb a2, 15(sp)
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; CHECK-NEXT: sb zero, 14(sp)
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; CHECK-NEXT: sb a3, 13(sp)
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; CHECK-NEXT: sb a0, 12(sp)
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; CHECK-NEXT: sb a1, 11(sp)
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; CHECK-NEXT: addi a1, zero, 1
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; CHECK-NEXT: sb a1, 10(sp)
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; CHECK-NEXT: sb a0, 9(sp)
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; CHECK-NEXT: sb a0, 8(sp)
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; CHECK-NEXT: vsetivli a0, 8, e8,mf2,ta,mu
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; CHECK-NEXT: addi a0, sp, 8
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; CHECK-NEXT: vle8.v v25, (a0)
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; CHECK-NEXT: vand.vi v25, v25, 1
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%1 = insertelement <8 x i1> undef, i1 %x, i32 0
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%2 = insertelement <8 x i1> %1, i1 %x, i32 1
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%3 = insertelement <8 x i1> %2, i1 1, i32 2
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%4 = insertelement <8 x i1> %3, i1 %y, i32 3
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%5 = insertelement <8 x i1> %4, i1 %x, i32 4
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%6 = insertelement <8 x i1> %5, i1 %w, i32 5
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%7 = insertelement <8 x i1> %6, i1 0, i32 6
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%8 = insertelement <8 x i1> %7, i1 %z, i32 7
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ret <8 x i1> %8
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}
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define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1(i1 %x, i1 %y) optsize {
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; CHECK-LABEL: buildvec_mask_optsize_nonconst_v8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: sb a1, 15(sp)
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; CHECK-NEXT: sb a1, 14(sp)
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; CHECK-NEXT: sb a1, 13(sp)
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; CHECK-NEXT: sb a0, 12(sp)
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; CHECK-NEXT: sb a1, 11(sp)
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; CHECK-NEXT: sb a1, 10(sp)
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; CHECK-NEXT: sb a0, 9(sp)
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; CHECK-NEXT: sb a0, 8(sp)
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; CHECK-NEXT: vsetivli a0, 8, e8,mf2,ta,mu
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; CHECK-NEXT: addi a0, sp, 8
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; CHECK-NEXT: vle8.v v25, (a0)
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; CHECK-NEXT: vand.vi v25, v25, 1
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; CHECK-NEXT: vmsne.vi v0, v25, 0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%1 = insertelement <8 x i1> undef, i1 %x, i32 0
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%2 = insertelement <8 x i1> %1, i1 %x, i32 1
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%3 = insertelement <8 x i1> %2, i1 %y, i32 2
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%4 = insertelement <8 x i1> %3, i1 %y, i32 3
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%5 = insertelement <8 x i1> %4, i1 %x, i32 4
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%6 = insertelement <8 x i1> %5, i1 %y, i32 5
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%7 = insertelement <8 x i1> %6, i1 %y, i32 6
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%8 = insertelement <8 x i1> %7, i1 %y, i32 7
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ret <8 x i1> %8
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}
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|
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define <10 x i1> @buildvec_mask_v10i1() {
|
||||
; CHECK-LABEL: buildvec_mask_v10i1:
|
||||
; CHECK: # %bb.0:
|
||||
@ -518,13 +761,13 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
|
||||
;
|
||||
; RV32-LMULMAX4-LABEL: buildvec_mask_optsize_v128i1:
|
||||
; RV32-LMULMAX4: # %bb.0:
|
||||
; RV32-LMULMAX4-NEXT: lui a0, %hi(.LCPI10_0)
|
||||
; RV32-LMULMAX4-NEXT: addi a0, a0, %lo(.LCPI10_0)
|
||||
; RV32-LMULMAX4-NEXT: lui a0, %hi(.LCPI21_0)
|
||||
; RV32-LMULMAX4-NEXT: addi a0, a0, %lo(.LCPI21_0)
|
||||
; RV32-LMULMAX4-NEXT: addi a1, zero, 64
|
||||
; RV32-LMULMAX4-NEXT: vsetvli a1, a1, e8,m4,ta,mu
|
||||
; RV32-LMULMAX4-NEXT: vle1.v v0, (a0)
|
||||
; RV32-LMULMAX4-NEXT: lui a0, %hi(.LCPI10_1)
|
||||
; RV32-LMULMAX4-NEXT: addi a0, a0, %lo(.LCPI10_1)
|
||||
; RV32-LMULMAX4-NEXT: lui a0, %hi(.LCPI21_1)
|
||||
; RV32-LMULMAX4-NEXT: addi a0, a0, %lo(.LCPI21_1)
|
||||
; RV32-LMULMAX4-NEXT: vle1.v v8, (a0)
|
||||
; RV32-LMULMAX4-NEXT: ret
|
||||
;
|
||||
@ -551,8 +794,8 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
|
||||
;
|
||||
; RV32-LMULMAX8-LABEL: buildvec_mask_optsize_v128i1:
|
||||
; RV32-LMULMAX8: # %bb.0:
|
||||
; RV32-LMULMAX8-NEXT: lui a0, %hi(.LCPI10_0)
|
||||
; RV32-LMULMAX8-NEXT: addi a0, a0, %lo(.LCPI10_0)
|
||||
; RV32-LMULMAX8-NEXT: lui a0, %hi(.LCPI21_0)
|
||||
; RV32-LMULMAX8-NEXT: addi a0, a0, %lo(.LCPI21_0)
|
||||
; RV32-LMULMAX8-NEXT: addi a1, zero, 128
|
||||
; RV32-LMULMAX8-NEXT: vsetvli a1, a1, e8,m8,ta,mu
|
||||
; RV32-LMULMAX8-NEXT: vle1.v v0, (a0)
|
||||
@ -560,8 +803,8 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
|
||||
;
|
||||
; RV64-LMULMAX8-LABEL: buildvec_mask_optsize_v128i1:
|
||||
; RV64-LMULMAX8: # %bb.0:
|
||||
; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI10_0)
|
||||
; RV64-LMULMAX8-NEXT: addi a0, a0, %lo(.LCPI10_0)
|
||||
; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI21_0)
|
||||
; RV64-LMULMAX8-NEXT: addi a0, a0, %lo(.LCPI21_0)
|
||||
; RV64-LMULMAX8-NEXT: addi a1, zero, 128
|
||||
; RV64-LMULMAX8-NEXT: vsetvli a1, a1, e8,m8,ta,mu
|
||||
; RV64-LMULMAX8-NEXT: vle1.v v0, (a0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user