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[mips] Disable code generation through FastISel for MIPS32R6.
Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14708 llvm-svn: 253225
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@ -192,10 +192,10 @@ public:
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TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
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MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
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Context = &funcInfo.Fn->getContext();
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bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32();
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TargetSupported =
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((TM.getRelocationModel() == Reloc::PIC_) &&
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((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
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(static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
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ISASupported && (TM.getRelocationModel() == Reloc::PIC_) &&
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(static_cast<const MipsTargetMachine &>(TM).getABI().IsO32());
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UnsupportedFPMode = Subtarget->isFP64bit();
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}
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27
test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
Normal file
27
test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
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@ -0,0 +1,27 @@
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; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \
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; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic \
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; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic \
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; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
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; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \
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; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic \
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; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic \
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; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic \
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; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
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; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
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; CHECK: FastISel missed terminator: ret i32 0
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define i32 @foo() {
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entry:
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ret i32 0
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}
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