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update a bunch of entries.
llvm-svn: 122700
This commit is contained in:
Chris Lattner
parent
2d1c116071
commit
222b24e2de
@ -2,38 +2,6 @@ Target Independent Opportunities:
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//===---------------------------------------------------------------------===//
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We should recognize idioms for add-with-carry and turn it into the appropriate
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intrinsics. This example:
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unsigned add32carry(unsigned sum, unsigned x) {
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unsigned z = sum + x;
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if (sum + x < x)
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z++;
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return z;
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}
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Compiles to: clang t.c -S -o - -O3 -fomit-frame-pointer -m64 -mkernel
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_add32carry: ## @add32carry
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addl %esi, %edi
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cmpl %esi, %edi
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sbbl %eax, %eax
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andl $1, %eax
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addl %edi, %eax
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ret
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with clang, but to:
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_add32carry:
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leal (%rsi,%rdi), %eax
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cmpl %esi, %eax
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adcl $0, %eax
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ret
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with gcc.
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//===---------------------------------------------------------------------===//
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Dead argument elimination should be enhanced to handle cases when an argument is
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dead to an externally visible function. Though the argument can't be removed
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from the externally visible function, the caller doesn't need to pass it in.
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@ -82,6 +50,9 @@ unsigned int mul(unsigned int a,unsigned int b) {
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return a*b;
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}
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The legalization code for mul-with-overflow needs to be made more robust before
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this can be implemented though.
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//===---------------------------------------------------------------------===//
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Get the C front-end to expand hypot(x,y) -> llvm.sqrt(x*x+y*y) when errno and
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@ -92,41 +63,6 @@ right).
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//===---------------------------------------------------------------------===//
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Solve this DAG isel folding deficiency:
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int X, Y;
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void fn1(void)
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{
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X = X | (Y << 3);
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}
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compiles to
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fn1:
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movl Y, %eax
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shll $3, %eax
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orl X, %eax
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movl %eax, X
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ret
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The problem is the store's chain operand is not the load X but rather
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a TokenFactor of the load X and load Y, which prevents the folding.
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There are two ways to fix this:
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1. The dag combiner can start using alias analysis to realize that y/x
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don't alias, making the store to X not dependent on the load from Y.
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2. The generated isel could be made smarter in the case it can't
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disambiguate the pointers.
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Number 1 is the preferred solution.
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This has been "fixed" by a TableGen hack. But that is a short term workaround
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which will be removed once the proper fix is made.
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//===---------------------------------------------------------------------===//
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On targets with expensive 64-bit multiply, we could LSR this:
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for (i = ...; ++i) {
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@ -339,14 +275,6 @@ unsigned long reverse(unsigned v) {
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return v ^ (t >> 8);
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}
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Neither is this (very standard idiom):
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int f(int n)
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{
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return (((n) << 24) | (((n) & 0xff00) << 8)
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| (((n) >> 8) & 0xff00) | ((n) >> 24));
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}
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//===---------------------------------------------------------------------===//
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[LOOP RECOGNITION]
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@ -382,9 +310,7 @@ unsigned int popcount(unsigned int input) {
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return count;
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}
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This is a form of idiom recognition for loops, the same thing that could be
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useful for recognizing memset/memcpy. This sort of thing should be added to the
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loop idiom pass.
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This sort of thing should be added to the loop idiom pass.
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//===---------------------------------------------------------------------===//
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@ -639,46 +565,21 @@ struct THotKey { short Key; bool Control; bool Shift; bool Alt; };
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extern THotKey m_HotKey;
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THotKey GetHotKey () { return m_HotKey; }
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into (-O3 -fno-exceptions -static -fomit-frame-pointer):
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into (-m64 -O3 -fno-exceptions -static -fomit-frame-pointer):
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__Z9GetHotKeyv:
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pushl %esi
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movl 8(%esp), %eax
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movb _m_HotKey+3, %cl
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movb _m_HotKey+4, %dl
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movb _m_HotKey+2, %ch
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movw _m_HotKey, %si
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movw %si, (%eax)
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movb %ch, 2(%eax)
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movb %cl, 3(%eax)
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movb %dl, 4(%eax)
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popl %esi
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ret $4
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GCC produces:
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__Z9GetHotKeyv:
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movl _m_HotKey, %edx
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movl 4(%esp), %eax
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movl %edx, (%eax)
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movzwl _m_HotKey+4, %edx
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movw %dx, 4(%eax)
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ret $4
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The LLVM IR contains the needed alignment info, so we should be able to
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merge the loads and stores into 4-byte loads:
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%struct.THotKey = type { i16, i8, i8, i8 }
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define void @_Z9GetHotKeyv(%struct.THotKey* sret %agg.result) nounwind {
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...
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%tmp2 = load i16* getelementptr (@m_HotKey, i32 0, i32 0), align 8
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%tmp5 = load i8* getelementptr (@m_HotKey, i32 0, i32 1), align 2
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%tmp8 = load i8* getelementptr (@m_HotKey, i32 0, i32 2), align 1
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%tmp11 = load i8* getelementptr (@m_HotKey, i32 0, i32 3), align 2
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Alternatively, we should use a small amount of base-offset alias analysis
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to make it so the scheduler doesn't need to hold all the loads in regs at
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once.
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__Z9GetHotKeyv: ## @_Z9GetHotKeyv
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movq _m_HotKey@GOTPCREL(%rip), %rax
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movzwl (%rax), %ecx
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movzbl 2(%rax), %edx
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shlq $16, %rdx
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orq %rcx, %rdx
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movzbl 3(%rax), %ecx
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shlq $24, %rcx
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orq %rdx, %rcx
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movzbl 4(%rax), %eax
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shlq $32, %rax
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orq %rcx, %rax
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ret
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//===---------------------------------------------------------------------===//
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@ -764,20 +665,6 @@ etc. On X86, we miss a bunch of 'rotate by variable' cases because the rotate
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matching code in dag combine doesn't look through truncates aggressively
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enough. Here are some testcases reduces from GCC PR17886:
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unsigned long long f(unsigned long long x, int y) {
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return (x << y) | (x >> 64-y);
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}
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unsigned f2(unsigned x, int y){
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return (x << y) | (x >> 32-y);
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}
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unsigned long long f3(unsigned long long x){
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int y = 9;
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return (x << y) | (x >> 64-y);
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}
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unsigned f4(unsigned x){
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int y = 10;
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return (x << y) | (x >> 32-y);
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}
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unsigned long long f5(unsigned long long x, unsigned long long y) {
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return (x << 8) | ((y >> 48) & 0xffull);
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}
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@ -796,11 +683,6 @@ unsigned long long f6(unsigned long long x, unsigned long long y, int z) {
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}
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}
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On X86-64, we only handle f2/f3/f4 right. On x86-32, a few of these
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generate truly horrible code, instead of using shld and friends. On
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ARM, we end up with calls to L___lshrdi3/L___ashldi3 in f, which is
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badness. PPC64 misses f, f5 and f6. CellSPU aborts in isel.
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//===---------------------------------------------------------------------===//
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This (and similar related idioms):
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@ -1507,6 +1507,8 @@ loop, the value comes into the loop as two values, and
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RegsForValue::getCopyFromRegs doesn't know how to put an AssertSext on the
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constructed BUILD_PAIR which represents the cast value.
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This can be handled by making CodeGenPrepare sink the cast.
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//===---------------------------------------------------------------------===//
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Test instructions can be eliminated by using EFLAGS values from arithmetic
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@ -1847,3 +1849,38 @@ _foo:
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0 is the only unsigned number < 1.
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//===---------------------------------------------------------------------===//
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This code:
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%0 = type { i32, i1 }
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define i32 @add32carry(i32 %sum, i32 %x) nounwind readnone ssp {
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entry:
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%uadd = tail call %0 @llvm.uadd.with.overflow.i32(i32 %sum, i32 %x)
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%cmp = extractvalue %0 %uadd, 1
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%inc = zext i1 %cmp to i32
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%add = add i32 %x, %sum
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%z.0 = add i32 %add, %inc
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ret i32 %z.0
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}
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declare %0 @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
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compiles to:
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_add32carry: ## @add32carry
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addl %esi, %edi
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sbbl %ecx, %ecx
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movl %edi, %eax
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subl %ecx, %eax
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ret
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But it could be:
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_add32carry:
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leal (%rsi,%rdi), %eax
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cmpl %esi, %eax
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adcl $0, %eax
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ret
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//===---------------------------------------------------------------------===//
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