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[X86] Don't form masked vfpclass instruction from and+vfpclass unless the fpclass only has a single use.
llvm-svn: 358841
This commit is contained in:
Craig Topper
parent
ac0297e2f3
commit
2260f17f91
@ -2596,16 +2596,27 @@ let Predicates = [HasAVX512] in {
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// ----------------------------------------------------------------
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// FPClass
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def X86Vfpclasss_su : PatFrag<(ops node:$src1, node:$src2),
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(X86Vfpclasss node:$src1, node:$src2), [{
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return N->hasOneUse();
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}]>;
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def X86Vfpclass_su : PatFrag<(ops node:$src1, node:$src2),
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(X86Vfpclass node:$src1, node:$src2), [{
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return N->hasOneUse();
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}]>;
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//handle fpclass instruction mask = op(reg_scalar,imm)
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// op(mem_scalar,imm)
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multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr,
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X86FoldableSchedWrite sched, X86VectorVTInfo _,
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Predicate prd> {
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let Predicates = [prd], ExeDomain = _.ExeDomain in {
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def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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(ins _.RC:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
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[(set _.KRC:$dst,(X86Vfpclasss (_.VT _.RC:$src1),
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(i32 imm:$src2)))]>,
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Sched<[sched]>;
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def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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@ -2613,7 +2624,7 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr##_.Suffix#
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(and _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1),
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(X86Vfpclasss_su (_.VT _.RC:$src1),
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(i32 imm:$src2))))]>,
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EVEX_K, Sched<[sched]>;
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def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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@ -2621,7 +2632,7 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr##_.Suffix##
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,
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(OpNode _.ScalarIntMemCPat:$src1,
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(X86Vfpclasss _.ScalarIntMemCPat:$src1,
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(i32 imm:$src2)))]>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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@ -2629,7 +2640,7 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr##_.Suffix##
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(and _.KRCWM:$mask,
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(OpNode _.ScalarIntMemCPat:$src1,
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(X86Vfpclasss_su _.ScalarIntMemCPat:$src1,
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(i32 imm:$src2))))]>,
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EVEX_K, Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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@ -2638,14 +2649,14 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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//handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
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// fpclass(reg_vec, mem_vec, imm)
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// fpclass(reg_vec, broadcast(eltVt), imm)
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multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
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X86FoldableSchedWrite sched, X86VectorVTInfo _,
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string mem, string broadcast>{
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let ExeDomain = _.ExeDomain in {
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def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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(ins _.RC:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
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[(set _.KRC:$dst,(X86Vfpclass (_.VT _.RC:$src1),
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(i32 imm:$src2)))]>,
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Sched<[sched]>;
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def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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@ -2653,14 +2664,14 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr##_.Suffix#
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(and _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1),
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(X86Vfpclass_su (_.VT _.RC:$src1),
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(i32 imm:$src2))))]>,
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EVEX_K, Sched<[sched]>;
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def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##mem#
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,(OpNode
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[(set _.KRC:$dst,(X86Vfpclass
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(_.VT (_.LdFrag addr:$src1)),
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(i32 imm:$src2)))]>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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@ -2668,7 +2679,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##mem#
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst, (and _.KRCWM:$mask, (OpNode
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[(set _.KRC:$dst, (and _.KRCWM:$mask, (X86Vfpclass_su
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(_.VT (_.LdFrag addr:$src1)),
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(i32 imm:$src2))))]>,
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EVEX_K, Sched<[sched.Folded, sched.ReadAfterFold]>;
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@ -2677,7 +2688,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
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_.BroadcastStr##", $dst|$dst, ${src1}"
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##_.BroadcastStr##", $src2}",
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[(set _.KRC:$dst,(OpNode
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[(set _.KRC:$dst,(X86Vfpclass
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(_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src1))),
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(i32 imm:$src2)))]>,
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@ -2687,7 +2698,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
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_.BroadcastStr##", $dst {${mask}}|$dst {${mask}}, ${src1}"##
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_.BroadcastStr##", $src2}",
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[(set _.KRC:$dst,(and _.KRCWM:$mask, (OpNode
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[(set _.KRC:$dst,(and _.KRCWM:$mask, (X86Vfpclass_su
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(_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src1))),
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(i32 imm:$src2))))]>,
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@ -2696,42 +2707,39 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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multiclass avx512_vector_fpclass_all<string OpcodeStr, AVX512VLVectorVTInfo _,
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bits<8> opc, SDNode OpNode,
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X86SchedWriteWidths sched, Predicate prd,
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string broadcast>{
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bits<8> opc, X86SchedWriteWidths sched,
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Predicate prd, string broadcast>{
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let Predicates = [prd] in {
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defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, sched.ZMM,
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defm Z : avx512_vector_fpclass<opc, OpcodeStr, sched.ZMM,
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_.info512, "{z}", broadcast>, EVEX_V512;
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}
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let Predicates = [prd, HasVLX] in {
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defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, sched.XMM,
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defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, sched.XMM,
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_.info128, "{x}", broadcast>, EVEX_V128;
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defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, sched.YMM,
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defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, sched.YMM,
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_.info256, "{y}", broadcast>, EVEX_V256;
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}
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}
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multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
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bits<8> opcScalar, SDNode VecOpNode,
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SDNode ScalarOpNode, X86SchedWriteWidths sched,
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bits<8> opcScalar, X86SchedWriteWidths sched,
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Predicate prd> {
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defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
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VecOpNode, sched, prd, "{l}">,
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sched, prd, "{l}">,
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EVEX_CD8<32, CD8VF>;
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defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
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VecOpNode, sched, prd, "{q}">,
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sched, prd, "{q}">,
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EVEX_CD8<64, CD8VF> , VEX_W;
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defm SSZ : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
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defm SSZ : avx512_scalar_fpclass<opcScalar, OpcodeStr,
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sched.Scl, f32x_info, prd>, VEX_LIG,
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EVEX_CD8<32, CD8VT1>;
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defm SDZ : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
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defm SDZ : avx512_scalar_fpclass<opcScalar, OpcodeStr,
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sched.Scl, f64x_info, prd>, VEX_LIG,
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EVEX_CD8<64, CD8VT1>, VEX_W;
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}
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defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
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X86Vfpclasss, SchedWriteFCmp, HasDQI>,
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AVX512AIi8Base, EVEX;
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defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, SchedWriteFCmp,
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HasDQI>, AVX512AIi8Base, EVEX;
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//-----------------------------------------------------------------
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// Mask register copy, including
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