RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

Remove a unused instruction itinerary class.

Browse Source 
llvm-svn: 114782
This commit is contained in:
Evan Cheng 2010-09-25 01:06:02 +00:00
parent 7dec569dfa
commit 2279dc1d2a
4 changed files with 0 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/ARM/ARMSchedule.td
View File

@ -17,7 +17,6 @@ def IIC_iALUsi : InstrItinClass;
def IIC_iALUsr : InstrItinClass;
def IIC_iUNAr : InstrItinClass;
def IIC_iUNAsi : InstrItinClass;
def IIC_iUNAsr : InstrItinClass;
def IIC_iEXTr : InstrItinClass;
def IIC_iEXTAr : InstrItinClass;
def IIC_iCMPi : InstrItinClass;

1
lib/Target/ARM/ARMScheduleA8.td
View File

@ -40,7 +40,6 @@ def CortexA8Itineraries : ProcessorItineraries<
// Unary Instructions that produce a result
InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
InstrItinData<IIC_iUNAsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
//
// Zero and sign extension instructions
InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,

1
lib/Target/ARM/ARMScheduleA9.td
View File

@ -50,7 +50,6 @@ def CortexA9Itineraries : ProcessorItineraries<
// Unary Instructions that produce a result
InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,
InstrItinData<IIC_iUNAsi , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
InstrItinData<IIC_iUNAsr , [InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 1, 1]>,
//
// Zero and sign extension instructions
InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,

1
lib/Target/ARM/ARMScheduleV6.td
View File

@ -33,7 +33,6 @@ def ARMV6Itineraries : ProcessorItineraries<
// Unary Instructions that produce a result
InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
InstrItinData<IIC_iUNAsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
//
// Zero and sign extension instructions
InstrItinData<IIC_iEXTr , [InstrStage<1, [V6_Pipe]>], [1, 1]>,