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https://github.com/RPCS3/llvm-mirror.git
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AMDGPU: Don't sometimes allow instructions before lowered si_end_cf
Since 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f, this would sometimes not emit the or to exec at the beginning of the block, where it really has to be. If there is an instruction that defines one of the source operands, split the block and turn the si_end_cf into a terminator. This avoids regressions when regalloc fast is switched to inserting reloads at the beginning of the block, instead of spills at the end of the block. In a future change, this should always split the block.
This commit is contained in:
Matt Arsenault
parent
09bd06838e
commit
22a074ddad
@ -1659,7 +1659,11 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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// register allocation.
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MI.setDesc(get(AMDGPU::S_XOR_B32));
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break;
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case AMDGPU::S_OR_B64_term:
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// This is only a terminator to get the correct spill code placement during
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// register allocation.
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MI.setDesc(get(AMDGPU::S_OR_B64));
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break;
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case AMDGPU::S_OR_B32_term:
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// This is only a terminator to get the correct spill code placement during
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// register allocation.
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@ -2236,6 +2240,7 @@ bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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case AMDGPU::SI_MASK_BRANCH:
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case AMDGPU::S_MOV_B64_term:
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case AMDGPU::S_XOR_B64_term:
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case AMDGPU::S_OR_B64_term:
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case AMDGPU::S_ANDN2_B64_term:
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case AMDGPU::S_MOV_B32_term:
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case AMDGPU::S_XOR_B32_term:
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@ -264,6 +264,7 @@ class WrapTerminatorInst<SOP_Pseudo base_inst> : SPseudoInstSI<
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let WaveSizePredicate = isWave64 in {
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def S_MOV_B64_term : WrapTerminatorInst<S_MOV_B64>;
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def S_XOR_B64_term : WrapTerminatorInst<S_XOR_B64>;
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def S_OR_B64_term : WrapTerminatorInst<S_OR_B64>;
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def S_ANDN2_B64_term : WrapTerminatorInst<S_ANDN2_B64>;
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}
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@ -99,6 +99,7 @@ private:
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unsigned MovTermOpc;
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unsigned Andn2TermOpc;
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unsigned XorTermrOpc;
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unsigned OrTermrOpc;
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unsigned OrSaveExecOpc;
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unsigned Exec;
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@ -106,7 +107,10 @@ private:
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void emitElse(MachineInstr &MI);
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void emitIfBreak(MachineInstr &MI);
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void emitLoop(MachineInstr &MI);
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void emitEndCf(MachineInstr &MI);
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MachineBasicBlock *splitBlock(MachineInstr &MI, MachineBasicBlock *BB,
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LiveIntervals *LIS);
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MachineBasicBlock *emitEndCf(MachineInstr &MI);
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void findMaskOperands(MachineInstr &MI, unsigned OpNo,
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SmallVectorImpl<MachineOperand> &Src) const;
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@ -115,7 +119,7 @@ private:
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bool removeMBBifRedundant(MachineBasicBlock &MBB);
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void process(MachineInstr &MI);
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MachineBasicBlock *process(MachineInstr &MI);
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// Skip to the next instruction, ignoring debug instructions, and trivial
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// block boundaries (blocks that have one (typically fallthrough) successor,
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@ -489,19 +493,73 @@ SILowerControlFlow::skipIgnoreExecInstsTrivialSucc(
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} while (true);
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}
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void SILowerControlFlow::emitEndCf(MachineInstr &MI) {
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MachineBasicBlock *SILowerControlFlow::splitBlock(MachineInstr &MI,
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MachineBasicBlock *BB,
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LiveIntervals *LIS) {
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MachineBasicBlock::iterator SplitPoint(&MI);
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++SplitPoint;
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if (SplitPoint == BB->end()) {
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// Don't bother with a new block.
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return BB;
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}
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// Make sure we add any physregs we define in the block as liveins to the new
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// block.
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LivePhysRegs LiveRegs(*TRI);
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LiveRegs.addLiveOuts(*BB);
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for (auto I = BB->rbegin(), E = SplitPoint.getReverse(); I != E; ++I)
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LiveRegs.stepBackward(*I);
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MachineFunction *MF = BB->getParent();
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MachineBasicBlock *SplitBB
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= MF->CreateMachineBasicBlock(BB->getBasicBlock());
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MF->insert(++MachineFunction::iterator(BB), SplitBB);
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SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
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SplitBB->transferSuccessorsAndUpdatePHIs(BB);
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BB->addSuccessor(SplitBB);
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addLiveIns(*SplitBB, LiveRegs);
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if (LIS)
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LIS->insertMBBInMaps(SplitBB, &MI);
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return SplitBB;
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}
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MachineBasicBlock *SILowerControlFlow::emitEndCf(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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Register CFMask = MI.getOperand(0).getReg();
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MachineInstr *Def = MRI.getUniqueVRegDef(CFMask);
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const DebugLoc &DL = MI.getDebugLoc();
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MachineBasicBlock::iterator InsPt =
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Def && Def->getParent() == &MBB ? std::next(MachineBasicBlock::iterator(Def))
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: MBB.begin();
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MachineInstr *NewMI = BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)
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.addReg(Exec)
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.add(MI.getOperand(0));
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MachineBasicBlock::iterator InsPt = MBB.begin();
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// If we have instructions that aren't prolog instructions, split the block
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// and emit a terminator instruction. This ensures correct spill placement.
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// FIXME: We should unconditionally split the block here.
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bool NeedBlockSplit = false;
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Register DataReg = MI.getOperand(0).getReg();
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for (MachineBasicBlock::iterator I = InsPt, E = MI.getIterator();
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I != E; ++I) {
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if (I->modifiesRegister(DataReg, TRI)) {
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NeedBlockSplit = true;
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break;
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}
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}
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unsigned Opcode = OrOpc;
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MachineBasicBlock *SplitBB = &MBB;
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if (NeedBlockSplit) {
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SplitBB = splitBlock(MI, &MBB, LIS);
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Opcode = OrTermrOpc;
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InsPt = MI;
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}
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MachineInstr *NewMI =
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BuildMI(MBB, InsPt, DL, TII->get(Opcode), Exec)
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.addReg(Exec)
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.add(MI.getOperand(0));
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LoweredEndCf.insert(NewMI);
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@ -522,6 +580,7 @@ void SILowerControlFlow::emitEndCf(MachineInstr &MI) {
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if (LIS)
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LIS->handleMove(*NewMI);
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return SplitBB;
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}
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// Returns replace operands for a logical operation, either single result
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@ -608,11 +667,13 @@ void SILowerControlFlow::optimizeEndCf() {
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}
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}
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void SILowerControlFlow::process(MachineInstr &MI) {
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MachineBasicBlock *SILowerControlFlow::process(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock::iterator I(MI);
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MachineInstr *Prev = (I != MBB.begin()) ? &*(std::prev(I)) : nullptr;
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MachineBasicBlock *SplitBB = &MBB;
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switch (MI.getOpcode()) {
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case AMDGPU::SI_IF:
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emitIf(MI);
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@ -631,7 +692,7 @@ void SILowerControlFlow::process(MachineInstr &MI) {
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break;
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case AMDGPU::SI_END_CF:
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emitEndCf(MI);
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SplitBB = emitEndCf(MI);
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break;
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default:
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@ -656,6 +717,8 @@ void SILowerControlFlow::process(MachineInstr &MI) {
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break;
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}
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}
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return SplitBB;
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}
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bool SILowerControlFlow::removeMBBifRedundant(MachineBasicBlock &MBB) {
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@ -718,6 +781,7 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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MovTermOpc = AMDGPU::S_MOV_B32_term;
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Andn2TermOpc = AMDGPU::S_ANDN2_B32_term;
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XorTermrOpc = AMDGPU::S_XOR_B32_term;
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OrTermrOpc = AMDGPU::S_OR_B32_term;
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OrSaveExecOpc = AMDGPU::S_OR_SAVEEXEC_B32;
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Exec = AMDGPU::EXEC_LO;
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} else {
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@ -727,6 +791,7 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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MovTermOpc = AMDGPU::S_MOV_B64_term;
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Andn2TermOpc = AMDGPU::S_ANDN2_B64_term;
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XorTermrOpc = AMDGPU::S_XOR_B64_term;
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OrTermrOpc = AMDGPU::S_OR_B64_term;
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OrSaveExecOpc = AMDGPU::S_OR_SAVEEXEC_B64;
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Exec = AMDGPU::EXEC;
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}
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@ -734,19 +799,21 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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SmallVector<MachineInstr *, 32> Worklist;
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MachineFunction::iterator NextBB;
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; BI = NextBB) {
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for (MachineFunction::iterator BI = MF.begin();
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BI != MF.end(); BI = NextBB) {
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NextBB = std::next(BI);
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MachineBasicBlock &MBB = *BI;
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MachineBasicBlock *MBB = &*BI;
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MachineBasicBlock::iterator I, Next;
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for (I = MBB.begin(); I != MBB.end(); I = Next) {
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MachineBasicBlock::iterator I, E, Next;
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E = MBB->end();
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for (I = MBB->begin(); I != E; I = Next) {
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Next = std::next(I);
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MachineInstr &MI = *I;
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MachineBasicBlock *SplitMBB = MBB;
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switch (MI.getOpcode()) {
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case AMDGPU::SI_IF:
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process(MI);
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SplitMBB = process(MI);
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break;
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case AMDGPU::SI_ELSE:
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@ -757,12 +824,17 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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if (InsertKillCleanups)
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Worklist.push_back(&MI);
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else
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process(MI);
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SplitMBB = process(MI);
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break;
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default:
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break;
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}
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if (SplitMBB != MBB) {
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MBB = Next->getParent();
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E = MBB->end();
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}
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}
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}
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@ -196,6 +196,12 @@ static bool removeTerminatorBit(const SIInstrInfo &TII, MachineInstr &MI) {
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MI.setDesc(TII.get(AMDGPU::S_XOR_B32));
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return true;
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}
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case AMDGPU::S_OR_B64_term: {
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// This is only a terminator to get the correct spill code placement during
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// register allocation.
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MI.setDesc(TII.get(AMDGPU::S_OR_B64));
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return true;
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}
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case AMDGPU::S_OR_B32_term: {
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// This is only a terminator to get the correct spill code placement during
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// register allocation.
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@ -205,9 +205,11 @@ body: |
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; CHECK: dead %7:vgpr_32 = GLOBAL_LOAD_DWORD undef %8:vreg_64, 0, 0, 0, 0, implicit $exec :: (volatile load 4, addrspace 1)
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; CHECK: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY [[COPY3]]
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; CHECK: bb.2:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY [[COPY4]]
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; CHECK: $exec = S_OR_B64 $exec, killed [[COPY5]], implicit-def $scc
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; CHECK: $exec = S_OR_B64_term $exec, killed [[COPY5]], implicit-def $scc
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; CHECK: bb.3:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: S_SLEEP 1
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; CHECK: [[COPY6:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
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; CHECK: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY6]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
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@ -1,18 +1,17 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=liveintervals,si-lower-control-flow,si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
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# Check that assert is not triggered
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...
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---
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name: si-lower-control-flow
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body: |
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bb.0:
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; GCN-LABEL: name: si-lower-control-flow
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
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; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0
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; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0, 0
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; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[S_LOAD_DWORD_IMM]], 255, implicit-def $scc
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; GCN: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 65535, [[S_AND_B32_]], implicit-def $scc
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; GCN: dead %3:sreg_32_xm0 = S_AND_B32 65535, [[S_AND_B32_]], implicit-def $scc
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; GCN: S_ENDPGM 0
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%0:sgpr_64 = COPY $sgpr4_sgpr5
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%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0, 0
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@ -51,3 +50,324 @@ body: |
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S_ENDPGM 0
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...
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# We need to split the block for SI_END_CF, but
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---
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name: end_cf_split_block_end
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: end_cf_split_block_end
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
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; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
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; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
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; GCN: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
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; GCN: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
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; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
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; GCN: S_BRANCH %bb.2
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; GCN: bb.1:
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; GCN: successors: %bb.2(0x80000000)
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; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]]
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; GCN: $exec = S_OR_B64_term $exec, [[COPY3]], implicit-def $scc
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; GCN: bb.2:
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; GCN: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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%0:vgpr_32 = COPY killed $vgpr0
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%1:vgpr_32 = COPY killed $vgpr1
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%3:sreg_64_xexec = V_CMP_EQ_U32_e64 killed %0, killed %1, implicit $exec
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%4:sreg_64_xexec = SI_IF %3, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
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%5:sreg_64_xexec = S_MOV_B64_term %4, implicit $exec
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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%6:sreg_64_xexec = COPY %5
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SI_END_CF killed %6, implicit-def $exec, implicit-def dead $scc, implicit $exec
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bb.2:
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S_ENDPGM 0
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...
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---
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name: end_cf_split_block_physreg_livein
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: end_cf_split_block_physreg_livein
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
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; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
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; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
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; GCN: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
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; GCN: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
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; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
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; GCN: S_BRANCH %bb.2
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; GCN: bb.1:
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; GCN: successors: %bb.3(0x80000000)
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; GCN: liveins: $vgpr0, $sgpr4_sgpr5
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]]
|
||||
; GCN: S_NOP 0
|
||||
; GCN: $exec = S_OR_B64_term $exec, [[COPY3]], implicit-def $scc
|
||||
; GCN: bb.3:
|
||||
; GCN: successors: %bb.2(0x80000000)
|
||||
; GCN: liveins: $vgpr0, $sgpr4_sgpr5
|
||||
; GCN: S_SLEEP 3
|
||||
; GCN: S_NOP 0, implicit $vgpr0, implicit $sgpr4_sgpr5
|
||||
; GCN: bb.2:
|
||||
; GCN: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5
|
||||
|
||||
%0:vgpr_32 = COPY killed $vgpr0
|
||||
%1:vgpr_32 = COPY killed $vgpr1
|
||||
%3:sreg_64_xexec = V_CMP_EQ_U32_e64 killed %0, killed %1, implicit $exec
|
||||
%4:sreg_64_xexec = SI_IF %3, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
%5:sreg_64_xexec = S_MOV_B64_term %4, implicit $exec
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
liveins: $vgpr0, $sgpr4_sgpr5
|
||||
|
||||
%6:sreg_64_xexec = COPY %5
|
||||
S_NOP 0
|
||||
SI_END_CF killed %6, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
S_SLEEP 3
|
||||
S_NOP 0, implicit $vgpr0, implicit $sgpr4_sgpr5
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: end_cf_split_block_physreg_livein_liveout
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: end_cf_split_block_physreg_livein_liveout
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x0000000000000003
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
|
||||
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
|
||||
; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
|
||||
; GCN: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
|
||||
; GCN: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
|
||||
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
|
||||
; GCN: S_BRANCH %bb.2
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.3(0x80000000)
|
||||
; GCN: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x0000000000000003
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]]
|
||||
; GCN: $exec = S_OR_B64_term $exec, [[COPY3]], implicit-def $scc
|
||||
; GCN: bb.3:
|
||||
; GCN: successors: %bb.2(0x80000000)
|
||||
; GCN: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr8_sgpr9
|
||||
; GCN: S_SLEEP 3
|
||||
; GCN: S_NOP 0
|
||||
; GCN: bb.2:
|
||||
; GCN: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x0000000000000003
|
||||
; GCN: S_ENDPGM 0, implicit $vgpr0, implicit $sgpr4_sgpr5, implicit $sgpr8_sgpr9_sgpr10_sgpr11
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x00000003
|
||||
|
||||
%0:vgpr_32 = COPY killed $vgpr0
|
||||
%1:vgpr_32 = COPY killed $vgpr1
|
||||
%3:sreg_64_xexec = V_CMP_EQ_U32_e64 killed %0, killed %1, implicit $exec
|
||||
%4:sreg_64_xexec = SI_IF %3, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
%5:sreg_64_xexec = S_MOV_B64_term %4, implicit $exec
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
liveins: $vgpr0, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x00000003
|
||||
|
||||
%6:sreg_64_xexec = COPY %5
|
||||
SI_END_CF killed %6, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
S_SLEEP 3
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
liveins: $vgpr0, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x00000003
|
||||
S_ENDPGM 0, implicit $vgpr0, implicit $sgpr4_sgpr5, implicit $sgpr8_sgpr9_sgpr10_sgpr11
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: end_cf_split_block_physreg_liveout
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: end_cf_split_block_physreg_liveout
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
|
||||
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
|
||||
; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
|
||||
; GCN: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
|
||||
; GCN: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
|
||||
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
|
||||
; GCN: S_BRANCH %bb.2
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.3(0x80000000)
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]]
|
||||
; GCN: $exec = S_OR_B64_term $exec, [[COPY3]], implicit-def $scc
|
||||
; GCN: bb.3:
|
||||
; GCN: successors: %bb.2(0x80000000)
|
||||
; GCN: liveins: $vgpr3
|
||||
; GCN: $vgpr3 = V_MOV_B32_e32 0, implicit $exec
|
||||
; GCN: $sgpr4_sgpr5 = S_MOV_B64 32
|
||||
; GCN: bb.2:
|
||||
; GCN: liveins: $vgpr3, $sgpr4_sgpr5
|
||||
; GCN: S_ENDPGM 0, implicit $vgpr3, implicit $sgpr4_sgpr5
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
|
||||
|
||||
%0:vgpr_32 = COPY killed $vgpr0
|
||||
%1:vgpr_32 = COPY killed $vgpr1
|
||||
%3:sreg_64_xexec = V_CMP_EQ_U32_e64 killed %0, killed %1, implicit $exec
|
||||
%4:sreg_64_xexec = SI_IF %3, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
%5:sreg_64_xexec = S_MOV_B64_term %4, implicit $exec
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
|
||||
%6:sreg_64_xexec = COPY %5
|
||||
SI_END_CF killed %6, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
$vgpr3 = V_MOV_B32_e32 0, implicit $exec
|
||||
$sgpr4_sgpr5 = S_MOV_B64 32
|
||||
|
||||
bb.2:
|
||||
liveins: $vgpr3, $sgpr4_sgpr5
|
||||
S_ENDPGM 0, implicit $vgpr3, implicit $sgpr4_sgpr5
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: end_cf_split_block_physreg_live_across_split
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: end_cf_split_block_physreg_live_across_split
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
|
||||
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
|
||||
; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
|
||||
; GCN: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
|
||||
; GCN: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
|
||||
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
|
||||
; GCN: S_BRANCH %bb.2
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.3(0x80000000)
|
||||
; GCN: liveins: $vgpr0, $sgpr4_sgpr5
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]]
|
||||
; GCN: $sgpr4_sgpr5 = S_MOV_B64 32
|
||||
; GCN: $exec = S_OR_B64_term $exec, [[COPY3]], implicit-def $scc
|
||||
; GCN: bb.3:
|
||||
; GCN: successors: %bb.2(0x80000000)
|
||||
; GCN: liveins: $vgpr0, $sgpr4_sgpr5
|
||||
; GCN: S_SLEEP 3, implicit $sgpr4_sgpr5
|
||||
; GCN: S_NOP 0
|
||||
; GCN: bb.2:
|
||||
; GCN: liveins: $vgpr0, $sgpr4_sgpr5
|
||||
; GCN: S_ENDPGM 0, implicit $vgpr0, implicit $sgpr4_sgpr5
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5
|
||||
|
||||
%0:vgpr_32 = COPY killed $vgpr0
|
||||
%1:vgpr_32 = COPY killed $vgpr1
|
||||
%3:sreg_64_xexec = V_CMP_EQ_U32_e64 killed %0, killed %1, implicit $exec
|
||||
%4:sreg_64_xexec = SI_IF %3, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
%5:sreg_64_xexec = S_MOV_B64_term %4, implicit $exec
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
liveins: $vgpr0, $sgpr4_sgpr5
|
||||
|
||||
%6:sreg_64_xexec = COPY %5
|
||||
$sgpr4_sgpr5 = S_MOV_B64 32
|
||||
SI_END_CF killed %6, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
S_SLEEP 3, implicit $sgpr4_sgpr5
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
liveins: $vgpr0, $sgpr4_sgpr5
|
||||
S_ENDPGM 0, implicit $vgpr0, implicit $sgpr4_sgpr5
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: end_cf_split_block_process_next_inst
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: end_cf_split_block_process_next_inst
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GCN: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY2]], implicit $exec
|
||||
; GCN: dead %5:sreg_64_xexec = S_MOV_B64 0
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.3(0x80000000)
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
|
||||
; GCN: $exec = S_OR_B64_term $exec, [[COPY3]], implicit-def $scc
|
||||
; GCN: bb.3:
|
||||
; GCN: successors: %bb.2(0x80000000)
|
||||
; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
|
||||
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
|
||||
; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY4]], implicit-def dead $scc
|
||||
; GCN: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
|
||||
; GCN: dead %8:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
|
||||
; GCN: S_CBRANCH_EXECZ %bb.2, implicit $exec
|
||||
; GCN: bb.2:
|
||||
; GCN: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
|
||||
%0:vgpr_32 = COPY killed $vgpr0
|
||||
%1:vgpr_32 = COPY killed $vgpr1
|
||||
%2:vgpr_32 = COPY killed $vgpr2
|
||||
%3:sreg_64_xexec = V_CMP_EQ_U32_e64 %0, killed %1, implicit $exec
|
||||
%4:sreg_64_xexec = V_CMP_EQ_U32_e64 killed %0, killed %2, implicit $exec
|
||||
%5:sreg_64_xexec = S_MOV_B64 0
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
|
||||
%6:sreg_64_xexec = COPY %3
|
||||
SI_END_CF killed %6, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
%7:sreg_64_xexec = SI_IF %4, %bb.2, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
%8:sreg_64_xexec = S_MOV_B64_term %7, implicit $exec
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue
Block a user