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[DAGCombiner] Stop visitEXTRACT_SUBVECTOR creating illegal BITCASTs post legalisation.

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visitEXTRACT_SUBVECTOR can sometimes create illegal BITCASTs when
removing "redundant" INSERT_SUBVECTOR operations.  This patch adds
an extra check to ensure such combines only occur after operation
legalisation if any resulting BITBAST is itself legal.

Differential Revision: https://reviews.llvm.org/D108086

(cherry picked from commit cd0e1964137f1cd7b508809ec80c7d9dcb3f0458)
This commit is contained in:
Paul Walker 2021-08-15 14:24:20 +01:00 committed by Tom Stellard
parent 0bbcb191e3
commit 22b0c02125
2 changed files with 36 additions and 1 deletions
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6
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -20560,8 +20560,12 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
// otherwise => (extract_subvec V1, ExtIdx)
uint64_t InsIdx = V.getConstantOperandVal(2);
if (InsIdx * SmallVT.getScalarSizeInBits() ==
ExtIdx * NVT.getScalarSizeInBits())
ExtIdx * NVT.getScalarSizeInBits()) {
if (LegalOperations && !TLI.isOperationLegal(ISD::BITCAST, NVT))
return SDValue();
return DAG.getBitcast(NVT, V.getOperand(1));
}
return DAG.getNode(
ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT,
DAG.getBitcast(N->getOperand(0).getValueType(), V.getOperand(0)),

31
test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
View File

@ -1057,6 +1057,37 @@ define void @masked_scatter_vec_plus_imm(<32 x float>* %a, <32 x i8*>* %b) #0 {
ret void
}
; extract_subvec(...(insert_subvec(a,b,c))) -> extract_subvec(bitcast(b),d) like
; combines can effectively unlegalise bitcast operations. This test ensures such
; combines do not happen after operation legalisation. When not prevented the
; test triggers infinite combine->legalise->combine->...
;
; NOTE: For this test to function correctly it's critical for %vals to be in a
; different block to the scatter store. If not, the problematic bitcast will be
; removed before operation legalisation and thus not exercise the combine.
define void @masked_scatter_bitcast_infinite_loop(<8 x double>* %a, <8 x double*>* %b, i1 %cond) #0 {
; CHECK-LABEL: masked_scatter_bitcast_infinite_loop
; VBITS_GE_512: ptrue [[PG0:p[0-9]+]].d, vl8
; VBITS_GE_512-NEXT: ld1d { [[VALS:z[0-9]+]].d }, [[PG0]]/z, [x0]
; VBITS_GE_512-NEXT: tbz w2, #0, [[LABEL:.*]]
; VBITS_GE_512-NEXT: ld1d { [[PTRS:z[0-9]+]].d }, [[PG0]]/z, [x1]
; VBITS_GE_512-NEXT: fcmeq [[MASK:p[0-9]+]].d, [[PG0]]/z, [[VALS]].d, #0.0
; VBITS_GE_512-NEXT: st1d { [[VALS]].d }, [[MASK]], {{\[}}[[PTRS]].d]
; VBITS_GE_512-NEXT: [[LABEL]]:
; VBITS_GE_512-NEXT: ret
%vals = load volatile <8 x double>, <8 x double>* %a
br i1 %cond, label %bb.1, label %bb.2
bb.1:
%ptrs = load <8 x double*>, <8 x double*>* %b
%mask = fcmp oeq <8 x double> %vals, zeroinitializer
call void @llvm.masked.scatter.v8f64(<8 x double> %vals, <8 x double*> %ptrs, i32 8, <8 x i1> %mask)
br label %bb.2
bb.2:
ret void
}
declare void @llvm.masked.scatter.v2i8(<2 x i8>, <2 x i8*>, i32, <2 x i1>)
declare void @llvm.masked.scatter.v4i8(<4 x i8>, <4 x i8*>, i32, <4 x i1>)
declare void @llvm.masked.scatter.v8i8(<8 x i8>, <8 x i8*>, i32, <8 x i1>)