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[SDAG] Use shift amount type in MULO promotion; NFC

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Directly use the correct shift amount type if it is possible, and
future-proof the code against vectors. The added test makes sure that
bitwidths that do not fit into the shift amount type do not assert.

Split out from D57997.

llvm-svn: 354359
This commit is contained in:
Nikita Popov 2019-02-19 17:37:55 +00:00
parent 35b8394f56
commit 22c4c72f33
2 changed files with 13 additions and 2 deletions
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6
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -952,9 +952,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
SDValue Overflow;
if (N->getOpcode() == ISD::UMULO) {
// Unsigned overflow occurred if the high part is non-zero.
unsigned Shift = SmallVT.getScalarSizeInBits();
EVT ShiftTy = getShiftAmountTyForConstant(Shift, Mul.getValueType(),
TLI, DAG);
SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
DL));
DAG.getConstant(Shift, DL, ShiftTy));
Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
DAG.getConstant(0, DL, Hi.getValueType()),
ISD::SETNE);

9
test/CodeGen/X86/umul-with-overflow.ll
View File

@ -68,3 +68,12 @@ entry:
%tmp2 = extractvalue { i32, i1 } %tmp1, 0
ret i32 %tmp2
}
; Check that shifts larger than the shift amount type are handled.
; Intentionally not testing codegen here, only that this doesn't assert.
declare {i300, i1} @llvm.umul.with.overflow.i300(i300 %a, i300 %b)
define i300 @test4(i300 %a, i300 %b) nounwind {
%x = call {i300, i1} @llvm.umul.with.overflow.i300(i300 %a, i300 %b)
%y = extractvalue {i300, i1} %x, 0
ret i300 %y
}