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[SelectionDAG] Add VT consistency checks to the creation of ISD::FMA.

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This is similar to what is done for binops. I don't know if this would have helped us catch the bug fixed in r336566 earlier or not, but I figured it couldn't hurt.

llvm-svn: 336576
This commit is contained in:
Craig Topper 2018-07-09 18:23:55 +00:00
parent 6df9a21e1d
commit 22ea0712b3
1 changed files with 3 additions and 0 deletions
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lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -4856,6 +4856,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
// Perform various simplifications.
switch (Opcode) {
case ISD::FMA: {
assert(VT.isFloatingPoint() && "This operator only applies to FP types!");
assert(N1.getValueType() == VT && N2.getValueType() == VT &&
N3.getValueType() == VT && "FMA types must match!");
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
ConstantFPSDNode *N3CFP = dyn_cast<ConstantFPSDNode>(N3);