mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-29 23:12:55 +01:00
Make SELECT illegal on PPC32, switch to using SELECT_CC, which more closely
reflects what the hardware is capable of. This significantly simplifies the CC handling logic throughout the ISel. llvm-svn: 22756
This commit is contained in:
Nate Begeman
parent
eddc9d4856
commit
23479935cc
@ -79,9 +79,14 @@ namespace {
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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}
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//PowerPC does not have CTPOP or CTTZ
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// PowerPC does not have CTPOP or CTTZ
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setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
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// PowerPC does not have Select
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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addLegalFPImmediate(+0.0); // Necessary for FSEL
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@ -564,11 +569,10 @@ public:
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unsigned getGlobalBaseReg();
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unsigned getConstDouble(double floatVal, unsigned Result);
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void MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result);
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void MoveCRtoGPR(unsigned CCReg, ISD::CondCode CC, unsigned Result);
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bool SelectBitfieldInsert(SDOperand OR, unsigned Result);
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unsigned FoldIfWideZeroExtend(SDOperand N);
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unsigned SelectCC(SDOperand CC, unsigned &Opc, bool &Inv, unsigned &Idx);
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unsigned SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv, unsigned &Idx);
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unsigned SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
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bool SelectIntImmediateExpr(SDOperand N, unsigned Result,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic = false, bool Negate = false);
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@ -689,21 +693,19 @@ static bool NodeHasRecordingVariant(unsigned NodeOpcode) {
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}
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/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
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/// to Condition. If the Condition is unordered or unsigned, the bool argument
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/// U is set to true, otherwise it is set to false.
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static unsigned getBCCForSetCC(unsigned Condition, bool& U) {
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U = false;
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switch (Condition) {
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/// to Condition.
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static unsigned getBCCForSetCC(ISD::CondCode CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition!"); abort();
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case ISD::SETEQ: return PPC::BEQ;
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case ISD::SETNE: return PPC::BNE;
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case ISD::SETULT: U = true;
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case ISD::SETULT:
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case ISD::SETLT: return PPC::BLT;
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case ISD::SETULE: U = true;
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case ISD::SETULE:
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case ISD::SETLE: return PPC::BLE;
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case ISD::SETUGT: U = true;
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case ISD::SETUGT:
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case ISD::SETGT: return PPC::BGT;
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case ISD::SETUGE: U = true;
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case ISD::SETUGE:
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case ISD::SETGE: return PPC::BGE;
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}
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return 0;
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@ -729,8 +731,8 @@ static unsigned getCROpForSetCC(unsigned Opcode, bool Inv1, bool Inv2) {
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/// getCRIdxForSetCC - Return the index of the condition register field
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/// associated with the SetCC condition, and whether or not the field is
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/// treated as inverted. That is, lt = 0; ge = 0 inverted.
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static unsigned getCRIdxForSetCC(unsigned Condition, bool& Inv) {
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switch (Condition) {
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static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
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switch (CC) {
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default: assert(0 && "Unknown condition!"); abort();
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case ISD::SETULT:
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case ISD::SETLT: Inv = false; return 0;
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@ -942,8 +944,10 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
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/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
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/// Inv is true, then invert the result.
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void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
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void ISel::MoveCRtoGPR(unsigned CCReg, ISD::CondCode CC, unsigned Result){
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bool Inv;
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unsigned IntCR = MakeReg(MVT::i32);
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unsigned Idx = getCRIdxForSetCC(CC, Inv);
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BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
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bool GPOpt =
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TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor();
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@ -1089,7 +1093,7 @@ unsigned ISel::FoldIfWideZeroExtend(SDOperand N) {
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return SelectExpr(N);
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}
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unsigned ISel::SelectCC(SDOperand Cond, unsigned& Opc, bool &Inv, unsigned& Idx) {
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unsigned ISel::SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC) {
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unsigned Result, Tmp1, Tmp2;
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bool AlreadySelected = false;
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static const unsigned CompareOpcodes[] =
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@ -1098,94 +1102,38 @@ unsigned ISel::SelectCC(SDOperand Cond, unsigned& Opc, bool &Inv, unsigned& Idx)
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// Allocate a condition register for this expression
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Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
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// If the first operand to the select is a SETCC node, then we can fold it
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// into the branch that selects which value to return.
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if (Cond.getOpcode() == ISD::SETCC) {
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ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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bool U;
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Opc = getBCCForSetCC(CC, U);
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Idx = getCRIdxForSetCC(CC, Inv);
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// Use U to determine whether the SETCC immediate range is signed or not.
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if (isIntImmediate(Cond.getOperand(1), Tmp2) &&
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((U && isUInt16(Tmp2)) || (!U && isInt16(Tmp2)))) {
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Tmp2 = Lo16(Tmp2);
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// For comparisons against zero, we can implicity set CR0 if a recording
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// variant (e.g. 'or.' instead of 'or') of the instruction that defines
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// operand zero of the SetCC node is available.
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if (Tmp2 == 0 &&
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NodeHasRecordingVariant(Cond.getOperand(0).getOpcode()) &&
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Cond.getOperand(0).Val->hasOneUse()) {
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RecordSuccess = false;
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Tmp1 = SelectExpr(Cond.getOperand(0), true);
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if (RecordSuccess) {
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++Recorded;
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BuildMI(BB, PPC::MCRF, 1, Result).addReg(PPC::CR0);
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return Result;
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}
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AlreadySelected = true;
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// Use U to determine whether the SETCC immediate range is signed or not.
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bool U = ISD::isUnsignedIntSetCC(CC);
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if (isIntImmediate(RHS, Tmp2) &&
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((U && isUInt16(Tmp2)) || (!U && isInt16(Tmp2)))) {
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Tmp2 = Lo16(Tmp2);
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// For comparisons against zero, we can implicity set CR0 if a recording
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// variant (e.g. 'or.' instead of 'or') of the instruction that defines
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// operand zero of the SetCC node is available.
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if (Tmp2 == 0 &&
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NodeHasRecordingVariant(LHS.getOpcode()) && LHS.Val->hasOneUse()) {
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RecordSuccess = false;
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Tmp1 = SelectExpr(LHS, true);
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if (RecordSuccess) {
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++Recorded;
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BuildMI(BB, PPC::MCRF, 1, Result).addReg(PPC::CR0);
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return Result;
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}
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// If we could not implicitly set CR0, then emit a compare immediate
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// instead.
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if (!AlreadySelected) Tmp1 = SelectExpr(Cond.getOperand(0));
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if (U)
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BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
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else
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BuildMI(BB, PPC::CMPWI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
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} else {
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bool IsInteger = MVT::isInteger(Cond.getOperand(0).getValueType());
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unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
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Tmp1 = SelectExpr(Cond.getOperand(0));
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Tmp2 = SelectExpr(Cond.getOperand(1));
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BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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AlreadySelected = true;
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}
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// If we could not implicitly set CR0, then emit a compare immediate
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// instead.
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if (!AlreadySelected) Tmp1 = SelectExpr(LHS);
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if (U)
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BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
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else
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BuildMI(BB, PPC::CMPWI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
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} else {
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// If this isn't a SetCC, then select the value and compare it against zero,
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// treating it as if it were a boolean.
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Opc = PPC::BNE;
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Idx = getCRIdxForSetCC(ISD::SETNE, Inv);
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Tmp1 = SelectExpr(Cond);
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BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
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}
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return Result;
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}
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unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
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unsigned &Idx) {
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bool Inv0, Inv1;
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unsigned Idx0, Idx1, CROpc, Opc1, Tmp1, Tmp2;
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// Allocate a condition register for this expression
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unsigned Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
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// Check for the operations we support:
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switch(N.getOpcode()) {
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default:
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Opc = PPC::BNE;
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Idx = getCRIdxForSetCC(ISD::SETNE, Inv);
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Tmp1 = SelectExpr(N);
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BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
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break;
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case ISD::OR:
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case ISD::AND:
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Tmp1 = SelectCCExpr(N.getOperand(0), Opc, Inv0, Idx0);
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Tmp2 = SelectCCExpr(N.getOperand(1), Opc1, Inv1, Idx1);
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CROpc = getCROpForSetCC(N.getOpcode(), Inv0, Inv1);
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if (Inv0 && !Inv1) {
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std::swap(Tmp1, Tmp2);
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std::swap(Idx0, Idx1);
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Opc = Opc1;
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}
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if (Inv0 && Inv1) Opc = PPC32InstrInfo::invertPPCBranchOpcode(Opc);
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BuildMI(BB, CROpc, 5, Result).addImm(Idx0).addReg(Tmp1).addImm(Idx0)
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.addReg(Tmp2).addImm(Idx1);
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Inv = false;
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Idx = Idx0;
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break;
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case ISD::SETCC:
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Tmp1 = SelectCC(N, Opc, Inv, Idx);
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Result = Tmp1;
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break;
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bool IsInteger = MVT::isInteger(LHS.getValueType());
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unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
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Tmp1 = SelectExpr(LHS);
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Tmp2 = SelectExpr(RHS);
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BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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return Result;
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}
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@ -1238,10 +1186,21 @@ void ISel::SelectBranchCC(SDOperand N)
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
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bool Inv;
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unsigned Opc, CCReg, Idx;
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Select(N.getOperand(0)); //chain
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CCReg = SelectCC(N.getOperand(1), Opc, Inv, Idx);
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// FIXME: Until we have Branch_CC and Branch_Twoway_CC, we're going to have to
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// Fake it up by hand by checking to see if op 1 is a SetCC, or a boolean.
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unsigned CCReg;
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ISD::CondCode CC;
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SDOperand Cond = N.getOperand(1);
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if (Cond.getOpcode() == ISD::SETCC) {
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CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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CCReg = SelectCC(Cond.getOperand(0), Cond.getOperand(1), CC);
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} else {
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CC = ISD::SETNE;
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CCReg = SelectCC(Cond, ISelDAG->getConstant(0, Cond.getValueType()), CC);
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}
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unsigned Opc = getBCCForSetCC(CC);
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// Iterate to the next basic block
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ilist<MachineBasicBlock>::iterator It = BB;
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@ -1374,7 +1333,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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switch (opcode) {
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default:
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Node->dump();
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assert(0 && "Node not handled!\n");
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assert(0 && "\nNode not handled!\n");
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case ISD::UNDEF:
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BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
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return Result;
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@ -2127,25 +2086,21 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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}
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}
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bool Inv;
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unsigned CCReg = SelectCC(N, Opc, Inv, Tmp2);
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MoveCRtoGPR(CCReg, Inv, Tmp2, Result);
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unsigned CCReg = SelectCC(N.getOperand(0), N.getOperand(1), CC);
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MoveCRtoGPR(CCReg, CC, Result);
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return Result;
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}
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case ISD::SELECT: {
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SDNode *Cond = N.getOperand(0).Val;
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ISD::CondCode CC;
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if (Cond->getOpcode() == ISD::SETCC &&
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!MVT::isInteger(N.getOperand(1).getValueType()) &&
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!MVT::isInteger(Cond->getOperand(1).getValueType()) &&
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cast<CondCodeSDNode>(Cond->getOperand(2))->get() != ISD::SETEQ &&
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cast<CondCodeSDNode>(Cond->getOperand(2))->get() != ISD::SETNE) {
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MVT::ValueType VT = Cond->getOperand(0).getValueType();
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ISD::CondCode CC = cast<CondCodeSDNode>(Cond->getOperand(2))->get();
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unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
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unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
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case ISD::SELECT_CC: {
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ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(4))->get();
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if (!MVT::isInteger(N.getOperand(0).getValueType()) &&
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!MVT::isInteger(N.getOperand(2).getValueType()) &&
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CC != ISD::SETEQ && CC != ISD::SETNE) {
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MVT::ValueType VT = N.getOperand(0).getValueType();
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unsigned TV = SelectExpr(N.getOperand(2)); // Use if TRUE
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unsigned FV = SelectExpr(N.getOperand(3)); // Use if FALSE
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Cond->getOperand(1));
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N.getOperand(1));
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if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
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switch(CC) {
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default: assert(0 && "Invalid FSEL condition"); abort();
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@ -2154,7 +2109,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
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case ISD::SETUGE:
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case ISD::SETGE:
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Tmp1 = SelectExpr(Cond->getOperand(0)); // Val to compare against
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Tmp1 = SelectExpr(N.getOperand(0)); // Val to compare against
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
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return Result;
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case ISD::SETUGT:
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@ -2162,11 +2117,11 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
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case ISD::SETULE:
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case ISD::SETLE: {
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if (Cond->getOperand(0).getOpcode() == ISD::FNEG) {
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Tmp2 = SelectExpr(Cond->getOperand(0).getOperand(0));
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if (N.getOperand(0).getOpcode() == ISD::FNEG) {
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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} else {
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Tmp2 = MakeReg(VT);
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Tmp1 = SelectExpr(Cond->getOperand(0)); // Val to compare against
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Tmp1 = SelectExpr(N.getOperand(0)); // Val to compare against
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BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
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}
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BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
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@ -2175,8 +2130,8 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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}
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} else {
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Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
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Tmp1 = SelectExpr(Cond->getOperand(0)); // Val to compare against
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Tmp2 = SelectExpr(Cond->getOperand(1));
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Tmp1 = SelectExpr(N.getOperand(0)); // Val to compare against
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Tmp2 = SelectExpr(N.getOperand(1));
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Tmp3 = MakeReg(VT);
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switch(CC) {
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default: assert(0 && "Invalid FSEL condition"); abort();
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@ -2205,11 +2160,11 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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assert(0 && "Should never get here");
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}
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bool Inv;
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unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
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unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
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unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
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unsigned TrueValue = SelectExpr(N.getOperand(2)); //Use if TRUE
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unsigned FalseValue = SelectExpr(N.getOperand(3)); //Use if FALSE
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unsigned CCReg = SelectCC(N.getOperand(0), N.getOperand(1), CC);
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Opc = getBCCForSetCC(CC);
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// Create an iterator with which to insert the MBB for copying the false
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// value and the MBB to hold the PHI instruction for this SetCC.
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MachineBasicBlock *thisMBB = BB;
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