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[AMDGPU] Update LiveVariables in convertToThreeAddress()
This can fix an asan failure like below.
==15856==ERROR: AddressSanitizer: use-after-poison on address ...
READ of size 8 at 0x6210001a3cb0 thread T0
#0 llvm::MachineInstr::getParent()
#1 llvm::LiveVariables::VarInfo::findKill()
#2 TwoAddressInstructionPass::rescheduleMIBelowKill()
#3 TwoAddressInstructionPass::tryInstructionTransform()
#4 TwoAddressInstructionPass::runOnMachineFunction()
We need to update the Kills if we replace instructions. The Kills
may be later accessed within TwoAddressInstruction pass.
Differential Revision: https://reviews.llvm.org/D89092
This commit is contained in:
Ruiling Song
parent
1e1e7e732e
commit
236d926c95
@ -15,10 +15,10 @@
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "GCNHazardRecognizer.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIDefines.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/ArrayRef.h"
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@ -28,6 +28,7 @@
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/MemoryLocation.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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@ -2841,6 +2842,18 @@ static int64_t getFoldableImm(const MachineOperand* MO) {
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return AMDGPU::NoRegister;
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}
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static void updateLiveVariables(LiveVariables *LV, MachineInstr &MI,
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MachineInstr &NewMI) {
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if (LV) {
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unsigned NumOps = MI.getNumOperands();
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for (unsigned I = 1; I < NumOps; ++I) {
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MachineOperand &Op = MI.getOperand(I);
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if (Op.isReg() && Op.isKill())
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LV->replaceKillInstruction(Op.getReg(), MI, NewMI);
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}
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}
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}
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MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
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MachineInstr &MI,
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LiveVariables *LV) const {
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@ -2888,43 +2901,53 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
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const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
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const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
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const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
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MachineInstrBuilder MIB;
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if (!Src0Mods && !Src1Mods && !Clamp && !Omod &&
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// If we have an SGPR input, we will violate the constant bus restriction.
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(ST.getConstantBusLimit(Opc) > 1 ||
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!Src0->isReg() ||
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(ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
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!RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
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if (auto Imm = getFoldableImm(Src2)) {
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unsigned NewOpc =
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IsFMA ? (IsF16 ? AMDGPU::V_FMAAK_F16 : AMDGPU::V_FMAAK_F32)
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: (IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32);
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if (pseudoToMCOpcode(NewOpc) != -1)
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return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
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.add(*Dst)
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.add(*Src0)
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.add(*Src1)
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.addImm(Imm);
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IsFMA ? (IsF16 ? AMDGPU::V_FMAAK_F16 : AMDGPU::V_FMAAK_F32)
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: (IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32);
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if (pseudoToMCOpcode(NewOpc) != -1) {
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MIB = BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
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.add(*Dst)
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.add(*Src0)
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.add(*Src1)
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.addImm(Imm);
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updateLiveVariables(LV, MI, *MIB);
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return MIB;
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}
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}
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unsigned NewOpc =
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IsFMA ? (IsF16 ? AMDGPU::V_FMAMK_F16 : AMDGPU::V_FMAMK_F32)
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: (IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32);
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unsigned NewOpc = IsFMA
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? (IsF16 ? AMDGPU::V_FMAMK_F16 : AMDGPU::V_FMAMK_F32)
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: (IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32);
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if (auto Imm = getFoldableImm(Src1)) {
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if (pseudoToMCOpcode(NewOpc) != -1)
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return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
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.add(*Dst)
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.add(*Src0)
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.addImm(Imm)
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.add(*Src2);
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if (pseudoToMCOpcode(NewOpc) != -1) {
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MIB = BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
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.add(*Dst)
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.add(*Src0)
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.addImm(Imm)
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.add(*Src2);
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updateLiveVariables(LV, MI, *MIB);
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return MIB;
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}
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}
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if (auto Imm = getFoldableImm(Src0)) {
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if (pseudoToMCOpcode(NewOpc) != -1 &&
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isOperandLegal(MI, AMDGPU::getNamedOperandIdx(NewOpc,
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AMDGPU::OpName::src0), Src1))
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return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
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.add(*Dst)
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.add(*Src1)
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.addImm(Imm)
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.add(*Src2);
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isOperandLegal(
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MI, AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::src0),
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Src1)) {
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MIB = BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
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.add(*Dst)
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.add(*Src1)
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.addImm(Imm)
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.add(*Src2);
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updateLiveVariables(LV, MI, *MIB);
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return MIB;
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}
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}
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}
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@ -2933,16 +2956,18 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
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if (pseudoToMCOpcode(NewOpc) == -1)
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return nullptr;
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return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
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.add(*Dst)
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.addImm(Src0Mods ? Src0Mods->getImm() : 0)
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.add(*Src0)
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.addImm(Src1Mods ? Src1Mods->getImm() : 0)
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.add(*Src1)
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.addImm(0) // Src mods
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.add(*Src2)
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.addImm(Clamp ? Clamp->getImm() : 0)
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.addImm(Omod ? Omod->getImm() : 0);
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MIB = BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
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.add(*Dst)
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.addImm(Src0Mods ? Src0Mods->getImm() : 0)
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.add(*Src0)
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.addImm(Src1Mods ? Src1Mods->getImm() : 0)
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.add(*Src1)
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.addImm(0) // Src mods
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.add(*Src2)
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.addImm(Clamp ? Clamp->getImm() : 0)
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.addImm(Omod ? Omod->getImm() : 0);
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updateLiveVariables(LV, MI, *MIB);
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return MIB;
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}
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// It's not generally safe to move VALU instructions across these since it will
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36
test/CodeGen/AMDGPU/stale-livevar-in-twoaddr-pass.mir
Normal file
36
test/CodeGen/AMDGPU/stale-livevar-in-twoaddr-pass.mir
Normal file
@ -0,0 +1,36 @@
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=livevars,phi-node-elimination,twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck %s
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# This used to fail under ASAN enabled build because we didn't update LiveVariables in SIInstrInfo::convertToThreeAddress()
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# CHECK: _amdgpu_ps_main
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---
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name: _amdgpu_ps_main
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alignment: 1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr2, $vgpr2, $vgpr3
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%0:vgpr_32 = COPY $vgpr3
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%1:vgpr_32 = COPY $vgpr2
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S_BRANCH %bb.3
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bb.1:
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%2:vgpr_32 = V_MAC_F32_e32 0, %0, %1, implicit $mode, implicit $exec
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%3:vgpr_32 = V_MED3_F32 0, %1, 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
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bb.2:
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%4:vgpr_32 = PHI %5, %bb.3, %3, %bb.1
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SI_END_CF %6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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EXP_DONE 0, %4, %4, %4, %4, -1, 0, 15, implicit $exec
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S_ENDPGM 0
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bb.3:
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successors: %bb.1, %bb.2
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%5:vgpr_32 = V_MAC_F32_e32 0, %1, %0, implicit $mode, implicit $exec
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%7:vgpr_32 = V_CVT_I32_F32_e32 %5, implicit $mode, implicit $exec
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%8:sreg_64 = V_CMP_NE_U32_e64 1, %7, implicit $exec
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%6:sreg_64 = SI_IF %8, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.1
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...
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