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[X86][SSE] Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG
Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 262599
This commit is contained in:
Simon Pilgrim
parent
22c3391de6
commit
2374787ea3
@ -273,6 +273,7 @@ namespace {
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SDValue visitANY_EXTEND(SDNode *N);
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SDValue visitSIGN_EXTEND_INREG(SDNode *N);
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SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
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SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
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SDValue visitTRUNCATE(SDNode *N);
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SDValue visitBITCAST(SDNode *N);
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SDValue visitBUILD_PAIR(SDNode *N);
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@ -1396,6 +1397,7 @@ SDValue DAGCombiner::visit(SDNode *N) {
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case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
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case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
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case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
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case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
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case ISD::TRUNCATE: return visitTRUNCATE(N);
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case ISD::BITCAST: return visitBITCAST(N);
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case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
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@ -5715,7 +5717,8 @@ static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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EVT VT = N->getValueType(0);
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assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
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Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
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Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
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Opcode == ISD::ZERO_EXTEND_VECTOR_INREG)
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&& "Expected EXTEND dag node in input!");
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// fold (sext c1) -> c1
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@ -6993,6 +6996,20 @@ SDValue DAGCombiner::visitSIGN_EXTEND_VECTOR_INREG(SDNode *N) {
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return SDValue();
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}
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SDValue DAGCombiner::visitZERO_EXTEND_VECTOR_INREG(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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if (N0.getOpcode() == ISD::UNDEF)
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return DAG.getUNDEF(VT);
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if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
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LegalOperations))
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return SDValue(Res, 0);
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return SDValue();
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}
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SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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@ -28332,13 +28332,15 @@ static SDValue getDivRem8(SDNode *N, SelectionDAG &DAG) {
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return R.getValue(1);
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}
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/// Convert a SEXT of a vector to a SIGN_EXTEND_VECTOR_INREG, this requires
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/// the splitting (or concatenating with UNDEFs) of the input to vectors of the
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/// same size as the target type which then extends the lowest elements.
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/// Convert a SEXT or ZEXT of a vector to a SIGN_EXTEND_VECTOR_INREG or
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/// ZERO_EXTEND_VECTOR_INREG, this requires the splitting (or concatenating
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/// with UNDEFs) of the input to vectors of the same size as the target type
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/// which then extends the lowest elements.
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static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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if (N->getOpcode() != ISD::SIGN_EXTEND)
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unsigned Opcode = N->getOpcode();
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if (Opcode != ISD::SIGN_EXTEND && Opcode != ISD::ZERO_EXTEND)
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return SDValue();
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if (!DCI.isBeforeLegalizeOps())
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return SDValue();
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@ -28359,6 +28361,12 @@ static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG,
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if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
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return SDValue();
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// On AVX2+ targets, if the input/output types are both legal then we will be
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// able to use SIGN_EXTEND/ZERO_EXTEND directly.
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if (Subtarget.hasInt256() && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
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DAG.getTargetLoweringInfo().isTypeLegal(InVT))
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return SDValue();
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SDLoc DL(N);
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auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
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@ -28378,20 +28386,22 @@ static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG,
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EVT ExVT =
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EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
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SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
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SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
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SDValue SExt = DAG.getNode(Opcode, DL, ExVT, Ex);
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
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DAG.getIntPtrConstant(0, DL));
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}
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// If target-size is 128-bits (or 256-bits on AVX2 target), then convert to
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// ISD::SIGN_EXTEND_VECTOR_INREG which ensures lowering to X86ISD::VSEXT.
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// ISD::*_EXTEND_VECTOR_INREG which ensures lowering to X86ISD::V*EXT.
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if (VT.is128BitVector() || (VT.is256BitVector() && Subtarget.hasInt256())) {
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SDValue ExOp = ExtendVecSize(DL, N0, VT.getSizeInBits());
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return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
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return Opcode == ISD::SIGN_EXTEND
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? DAG.getSignExtendVectorInReg(ExOp, DL, VT)
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: DAG.getZeroExtendVectorInReg(ExOp, DL, VT);
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}
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// On pre-AVX2 targets, split into 128-bit nodes of
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// ISD::SIGN_EXTEND_VECTOR_INREG.
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// ISD::*_EXTEND_VECTOR_INREG.
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if (!Subtarget.hasInt256() && !(VT.getSizeInBits() % 128)) {
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unsigned NumVecs = VT.getSizeInBits() / 128;
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unsigned NumSubElts = 128 / SVT.getSizeInBits();
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@ -28403,7 +28413,9 @@ static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG,
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SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
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DAG.getIntPtrConstant(Offset, DL));
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SrcVec = ExtendVecSize(DL, SrcVec, 128);
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SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
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SrcVec = Opcode == ISD::SIGN_EXTEND
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? DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT)
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: DAG.getZeroExtendVectorInReg(SrcVec, DL, SubVT);
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Opnds.push_back(SrcVec);
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}
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
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@ -28522,6 +28534,9 @@ static SDValue combineZext(SDNode *N, SelectionDAG &DAG,
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}
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}
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if (SDValue V = combineToExtendVectorInReg(N, DAG, DCI, Subtarget))
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return V;
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if (VT.is256BitVector())
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if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
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return R;
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@ -1428,11 +1428,10 @@ define <4 x float> @uitofp_16i8_to_4f32(<16 x i8> %a) {
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;
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; AVX1-LABEL: uitofp_16i8_to_4f32:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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@ -1752,18 +1751,16 @@ define <8 x float> @uitofp_8i8_to_8f32(<16 x i8> %a) {
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;
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; AVX1-LABEL: uitofp_8i8_to_8f32:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: uitofp_8i8_to_8f32:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
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; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
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; AVX2-NEXT: retq
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%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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@ -1786,11 +1783,10 @@ define <8 x float> @uitofp_16i8_to_8f32(<16 x i8> %a) {
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;
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; AVX1-LABEL: uitofp_16i8_to_8f32:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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@ -143,23 +143,20 @@ define <8 x i32> @zext_16i8_to_8i32(<16 x i8> %A) nounwind uwtable readnone ssp
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;
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; AVX1-LABEL: zext_16i8_to_8i32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: zext_16i8_to_8i32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
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; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: zext_16i8_to_8i32:
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; AVX512: # BB#0: # %entry
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; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
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; AVX512-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; AVX512-NEXT: retq
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entry:
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%B = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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@ -225,23 +222,20 @@ define <4 x i64> @zext_16i8_to_4i64(<16 x i8> %A) nounwind uwtable readnone ssp
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;
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; AVX1-LABEL: zext_16i8_to_4i64:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
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; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: zext_16i8_to_4i64:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
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; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: zext_16i8_to_4i64:
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; AVX512: # BB#0: # %entry
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; AVX512-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
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; AVX512-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; AVX512-NEXT: retq
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entry:
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%B = shufflevector <16 x i8> %A, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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@ -385,25 +379,20 @@ define <4 x i64> @zext_8i16_to_4i64(<8 x i16> %A) nounwind uwtable readnone ssp
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;
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; AVX1-LABEL: zext_8i16_to_4i64:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: zext_8i16_to_4i64:
|
||||
; AVX2: # BB#0: # %entry
|
||||
; AVX2-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
|
||||
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1
|
||||
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15]
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512-LABEL: zext_8i16_to_4i64:
|
||||
; AVX512: # BB#0: # %entry
|
||||
; AVX512-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
|
||||
; AVX512-NEXT: vpxor %ymm1, %ymm1, %ymm1
|
||||
; AVX512-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7],ymm0[8],ymm1[9,10,11],ymm0[12],ymm1[13,14,15]
|
||||
; AVX512-NEXT: retq
|
||||
entry:
|
||||
%B = shufflevector <8 x i16> %A, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user