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[NFC][InstCombine] Test what happens if 'unefficient high bit check' pattern is on both sides.

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Came up in https://reviews.llvm.org/D52001#1233827
While we don't do a good job here, we at least want to make
sure that we don't have any inf-loops.

llvm-svn: 342171
This commit is contained in:
Roman Lebedev 2018-09-13 20:33:02 +00:00
parent 0e8ba1b7ab
commit 2374d412bf
4 changed files with 60 additions and 0 deletions
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16
test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
View File

@ -102,6 +102,22 @@ define i1 @c0(i8 %bits) {
ret i1 %r
}
; What if we have the same pattern on both sides?
define i1 @both(i8 %bits0, i8 %bits1) {
; CHECK-LABEL: @both(
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
; CHECK-NEXT: [[T2:%.*]] = shl i8 -1, [[BITS1:%.*]]
; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T2]], [[T0]]
; CHECK-NEXT: ret i1 [[R]]
;
%t0 = shl i8 -1, %bits0
%t1 = xor i8 %t0, -1
%t2 = shl i8 -1, %bits1
%t3 = xor i8 %t2, -1
%r = icmp uge i8 %t1, %t3
ret i1 %r
}
; ============================================================================ ;
; One-use tests.
; ============================================================================ ;

14
test/Transforms/InstCombine/icmp-ugt-of-shl-1-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
View File

@ -68,6 +68,20 @@ define i1 @c0(i8 %bits) {
ret i1 %r
}
; What if we have the same pattern on both sides?
define i1 @both(i8 %bits0, i8 %bits1) {
; CHECK-LABEL: @both(
; CHECK-NEXT: [[T1:%.*]] = shl i8 1, [[BITS1:%.*]]
; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS0:%.*]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[T1_HIGHBITS]], 0
; CHECK-NEXT: ret i1 [[R]]
;
%t0 = shl i8 1, %bits0
%t1 = shl i8 1, %bits1
%r = icmp ugt i8 %t0, %t1
ret i1 %r
}
; ============================================================================ ;
; One-use tests.
; ============================================================================ ;

14
test/Transforms/InstCombine/icmp-ule-of-shl-1-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
View File

@ -68,6 +68,20 @@ define i1 @c0(i8 %bits) {
ret i1 %r
}
; What if we have the same pattern on both sides?
define i1 @both(i8 %bits0, i8 %bits1) {
; CHECK-LABEL: @both(
; CHECK-NEXT: [[T1:%.*]] = shl i8 1, [[BITS1:%.*]]
; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS0:%.*]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[T1_HIGHBITS]], 0
; CHECK-NEXT: ret i1 [[R]]
;
%t0 = shl i8 1, %bits0
%t1 = shl i8 1, %bits1
%r = icmp ule i8 %t0, %t1
ret i1 %r
}
; ============================================================================ ;
; One-use tests.
; ============================================================================ ;

16
test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
View File

@ -102,6 +102,22 @@ define i1 @c0(i8 %bits) {
ret i1 %r
}
; What if we have the same pattern on both sides?
define i1 @both(i8 %bits0, i8 %bits1) {
; CHECK-LABEL: @both(
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
; CHECK-NEXT: [[T2:%.*]] = shl i8 -1, [[BITS1:%.*]]
; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T2]], [[T0]]
; CHECK-NEXT: ret i1 [[R]]
;
%t0 = shl i8 -1, %bits0
%t1 = xor i8 %t0, -1
%t2 = shl i8 -1, %bits1
%t3 = xor i8 %t2, -1
%r = icmp ult i8 %t1, %t3
ret i1 %r
}
; ============================================================================ ;
; One-use tests.
; ============================================================================ ;