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Add some basic blackfin intrinsics.
llvm-svn: 77903
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@ -458,3 +458,4 @@ include "llvm/IntrinsicsARM.td"
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include "llvm/IntrinsicsCellSPU.td"
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include "llvm/IntrinsicsCellSPU.td"
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include "llvm/IntrinsicsAlpha.td"
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include "llvm/IntrinsicsAlpha.td"
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include "llvm/IntrinsicsXCore.td"
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include "llvm/IntrinsicsXCore.td"
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include "llvm/IntrinsicsBlackfin.td"
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51
include/llvm/IntrinsicsBlackfin.td
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51
include/llvm/IntrinsicsBlackfin.td
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//===- IntrinsicsBlackfin.td - Defines Blackfin intrinsics -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the blackfin-specific intrinsics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Core synchronisation etc.
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//
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// These intrinsics have sideeffects. Each represent a single instruction, but
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// workarounds are sometimes required depending on the cpu.
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let TargetPrefix = "bfin" in {
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// Execute csync instruction with workarounds
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def int_bfin_csync : GCCBuiltin<"__builtin_bfin_csync">,
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Intrinsic<[llvm_void_ty]>;
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// Execute ssync instruction with workarounds
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def int_bfin_ssync : GCCBuiltin<"__builtin_bfin_ssync">,
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Intrinsic<[llvm_void_ty]>;
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// Execute idle instruction with workarounds
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def int_bfin_idle : GCCBuiltin<"__builtin_bfin_idle">,
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Intrinsic<[llvm_void_ty]>;
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}
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//===----------------------------------------------------------------------===//
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// Miscellaneous GCC-compatible builtins.
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//
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let TargetPrefix = "bfin" in {
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// Almost identical to ctpop except for the type signature
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def int_bfin_ones : GCCBuiltin<"__builtin_bfin_ones">,
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Intrinsic<[llvm_i16_ty], [llvm_i32_ty], [IntrNoMem]>;
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// Load unaligned pointer, ignoring the low bits. Like *(p&~3).
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// This uses the disalignexcpt instruction
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def int_bfin_loadbytes : GCCBuiltin<"__builtin_bfin_loadbytes">,
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Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
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}
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@ -672,8 +672,9 @@ def NBITTST: F1<(outs JustCC:$cc), (ins D:$src1, uimm5mask:$src2),
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def ONES: F2<(outs D16L:$dst), (ins D:$src),
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def ONES: F2<(outs D16L:$dst), (ins D:$src),
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"$dst = ones $src;",
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"$dst = ones $src;",
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[(set D16L:$dst, (trunc (ctpop D:$src)))]>;
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[(set D16L:$dst, (int_bfin_ones D:$src))]>;
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def : Pat<(i16 (trunc (ctpop D:$src))), (ONES D:$src)>;
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def : Pat<(ctpop D:$src), (MOVEzext (ONES D:$src))>;
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def : Pat<(ctpop D:$src), (MOVEzext (ONES D:$src))>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -810,11 +811,51 @@ def MUL32: F1<(outs D:$dst), (ins D:$src1, D:$src2),
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// Table C-18. External Exent Management Instructions
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// Table C-18. External Exent Management Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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def IDLE : F1<(outs), (ins), "idle;", [(int_bfin_idle)]>;
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def CSYNC : F1<(outs), (ins), "csync;", [(int_bfin_csync)]>;
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def SSYNC : F1<(outs), (ins), "ssync;", [(int_bfin_ssync)]>;
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def EMUEXCPT : F1<(outs), (ins), "emuexcpt;", []>;
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def CLI : F1<(outs D:$mask), (ins), "cli $mask;", []>;
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def STI : F1<(outs), (ins D:$mask), "sti $mask;", []>;
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def RAISE : F1<(outs), (ins i32imm:$itr), "raise $itr;", []>;
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def EXCPT : F1<(outs), (ins i32imm:$exc), "excpt $exc;", []>;
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def NOP : F1<(outs), (ins), "nop;", []>;
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def MNOP : F2<(outs), (ins), "mnop;", []>;
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def ABORT : F1<(outs), (ins), "abort;", []>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Table C-19. Cache Control Instructions
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// Table C-19. Cache Control Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Table C-20. Video Pixel Operations Instructions
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// Table C-20. Video Pixel Operations Instructions
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//===----------------------------------------------------------------------===//
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def ALIGN8 : F2<(outs D:$dst), (ins D:$src1, D:$src2),
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"$dst = align8($src1, $src2);",
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[(set D:$dst, (or (shl D:$src1, (i32 24)),
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(srl D:$src2, (i32 8))))]>;
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def ALIGN16 : F2<(outs D:$dst), (ins D:$src1, D:$src2),
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"$dst = align16($src1, $src2);",
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[(set D:$dst, (or (shl D:$src1, (i32 16)),
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(srl D:$src2, (i32 16))))]>;
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def ALIGN24 : F2<(outs D:$dst), (ins D:$src1, D:$src2),
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"$dst = align16($src1, $src2);",
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[(set D:$dst, (or (shl D:$src1, (i32 8)),
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(srl D:$src2, (i32 24))))]>;
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def DISALGNEXCPT : F2<(outs), (ins), "disalignexcpt;", []>;
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// This is really two instructions in parallel, but we don't support vliw yet
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def DISALGNEXCPT_LOAD : F2<(outs D:$dst), (ins I:$ptr),
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"disalignexcpt \\|\\| $dst = [$ptr];",
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[(set D:$dst, (int_bfin_loadbytes I:$ptr))]>;
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// TODO: BYTEOP3P, BYTEOP16P, BYTEOP1P, BYTEOP2P, BYTEOP16M, SAA,
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// BYTEPACK, BYTEUNPACK
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// Table C-21. Vector Operations Instructions
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// Table C-21. Vector Operations Instructions
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// Patterns
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// Patterns
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16
test/CodeGen/Blackfin/load-intr.ll
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16
test/CodeGen/Blackfin/load-intr.ll
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; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs | FileCheck %s
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; XFAIL: *
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; Assertion failed: (isUsed(Reg) && "Using an undefined register!"),
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; function forward, file lib/CodeGen/RegisterScavenging.cpp, line 221.
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define i16 @f(i32* %p) nounwind {
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entry:
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; CHECK: disalignexcpt || r0 = [i0];
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%b = call i32 @llvm.bfin.loadbytes(i32* %p)
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; CHECK: r0.l = ones r0;
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%c = call i16 @llvm.bfin.ones(i32 %b)
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ret i16 %c
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}
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declare void @llvm.bfin.ones() nounwind
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declare void @llvm.bfin.loadbytes() nounwind
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13
test/CodeGen/Blackfin/sync-intr.ll
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13
test/CodeGen/Blackfin/sync-intr.ll
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; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs | FileCheck %s
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define void @f() nounwind {
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entry:
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; CHECK: csync;
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call void @llvm.bfin.csync()
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; CHECK: ssync;
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call void @llvm.bfin.ssync()
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ret void
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}
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declare void @llvm.bfin.csync() nounwind
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declare void @llvm.bfin.ssync() nounwind
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