From 24141f1c964d9103e9228980fa2782d6e5602b7a Mon Sep 17 00:00:00 2001 From: Jason Liu Date: Mon, 22 Jul 2019 19:55:33 +0000 Subject: [PATCH] [NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming convention Summary: Since we are planning to add ADDIStocHA for 32bit in later patch, we decided to change 64bit one first to follow naming convention with 8 behind opcode. Patch by: Xiangling_L Differential Revision: https://reviews.llvm.org/D64814 llvm-svn: 366731 --- lib/Target/PowerPC/P9InstrResources.td | 2 +- lib/Target/PowerPC/PPCAsmPrinter.cpp | 8 ++++---- lib/Target/PowerPC/PPCFastISel.cpp | 12 ++++++------ lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 8 ++++---- lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- lib/Target/PowerPC/PPCInstr64Bit.td | 4 ++-- lib/Target/PowerPC/PPCInstrInfo.cpp | 2 +- test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir | 4 ++-- test/CodeGen/PowerPC/aantidep-def-ec.mir | 2 +- test/CodeGen/PowerPC/licm-tocReg.ll | 10 +++++----- test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 2 +- test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir | 10 +++++----- 12 files changed, 33 insertions(+), 33 deletions(-) diff --git a/lib/Target/PowerPC/P9InstrResources.td b/lib/Target/PowerPC/P9InstrResources.td index 2a10322d3f4..3e2547882a6 100644 --- a/lib/Target/PowerPC/P9InstrResources.td +++ b/lib/Target/PowerPC/P9InstrResources.td @@ -148,7 +148,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C], (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(o)?$"), (instregex "ADD(4|8)(TLS)?(_)?$"), (instregex "NEG(8)?$"), - (instregex "ADDI(S)?toc(HA|L)$"), + (instregex "ADDI(S)?toc(HA|L)(8)?$"), COPY, MCRF, MCRXRX, diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 0646ddb73cd..237c8da1095 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -724,8 +724,8 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } - case PPC::ADDIStocHA: { - // Transform %xd = ADDIStocHA %x2, @sym + case PPC::ADDIStocHA8: { + // Transform %xd = ADDIStocHA8 %x2, @sym LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to ADDIS8. If the global address is external, has @@ -736,7 +736,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MachineOperand &MO = MI->getOperand(2); assert((MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isBlockAddress()) && - "Invalid operand for ADDIStocHA!"); + "Invalid operand for ADDIStocHA8!"); MCSymbol *MOSymbol = nullptr; bool GlobalToc = false; @@ -803,7 +803,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned char GVFlags = Subtarget->classifyGlobalReference(GV); assert((GVFlags & PPCII::MO_NLP_FLAG) && "LDtocL used on symbol that could be accessed directly is " - "invalid. Must match ADDIStocHA.")); + "invalid. Must match ADDIStocHA8.")); MOSymbol = lookUpOrCreateTOCEntry(MOSymbol); } diff --git a/lib/Target/PowerPC/PPCFastISel.cpp b/lib/Target/PowerPC/PPCFastISel.cpp index 264d6b590f9..2954b028f63 100644 --- a/lib/Target/PowerPC/PPCFastISel.cpp +++ b/lib/Target/PowerPC/PPCFastISel.cpp @@ -2031,8 +2031,8 @@ unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) .addImm(0).addReg(TmpReg).addMemOperand(MMO); } else { - // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)). - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA), + // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA8(X2, Idx)). + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8), TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx); // But for large code model, we must generate a LDtocL followed // by the LF[SD]. @@ -2085,12 +2085,12 @@ unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) { // or externally available linkage, a non-local function address, or a // jump table address (not yet needed), or if we are generating code // for large code model, we generate: - // LDtocL(GV, ADDIStocHA(%x2, GV)) + // LDtocL(GV, ADDIStocHA8(%x2, GV)) // Otherwise we generate: - // ADDItocL(ADDIStocHA(%x2, GV), GV) - // Either way, start with the ADDIStocHA: + // ADDItocL(ADDIStocHA8(%x2, GV), GV) + // Either way, start with the ADDIStocHA8: unsigned HighPartReg = createResultReg(RC); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA), + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8), HighPartReg).addReg(PPC::X2).addGlobalAddress(GV); unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV); diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 543cac075f5..2cb0387d9a9 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -5085,12 +5085,12 @@ void PPCDAGToDAGISel::Select(SDNode *N) { // The first source operand is a TargetGlobalAddress or a TargetJumpTable. // If it must be toc-referenced according to PPCSubTarget, we generate: - // LDtocL(@sym, ADDIStocHA(%x2, @sym)) + // LDtocL(@sym, ADDIStocHA8(%x2, @sym)) // Otherwise we generate: - // ADDItocL(ADDIStocHA(%x2, @sym), @sym) + // ADDItocL(ADDIStocHA8(%x2, @sym), @sym) SDValue GA = N->getOperand(0); SDValue TOCbase = N->getOperand(1); - SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64, + SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA8, dl, MVT::i64, TOCbase, GA); if (PPCLowering->isAccessedAsGotIndirect(GA)) { // If it is access as got-indirect, we need an extra LD to load @@ -6456,7 +6456,7 @@ void PPCDAGToDAGISel::PeepholePPC64() { continue; if (!HBase.isMachineOpcode() || - HBase.getMachineOpcode() != PPC::ADDIStocHA) + HBase.getMachineOpcode() != PPC::ADDIStocHA8) continue; if (!Base.hasOneUse() || !HBase.hasOneUse()) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 24d50074860..b1ab405e54f 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -14336,7 +14336,7 @@ bool PPCTargetLowering::isAccessedAsGotIndirect(SDValue GA) const { CodeModel::Model CModel = getTargetMachine().getCodeModel(); // If it is small or large code model, module locals are accessed // indirectly by loading their address from .toc/.got. The difference - // is that for large code model we have ADDISTocHa + LDtocL and for + // is that for large code model we have ADDIStocHA8 + LDtocL and for // small code model we simply have LDtoc. if (CModel == CodeModel::Small || CModel == CodeModel::Large) return true; diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index d598567f8e4..f16187149d3 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -1099,8 +1099,8 @@ def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), // Support for medium and large code model. let hasSideEffects = 0 in { let isReMaterializable = 1 in { -def ADDIStocHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), - "#ADDIStocHA", []>, isPPC64; +def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), + "#ADDIStocHA8", []>, isPPC64; def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), "#ADDItocL", []>, isPPC64; } diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index a787bdd56b9..2d6b1359a3a 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -329,7 +329,7 @@ bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, case PPC::LIS: case PPC::LIS8: case PPC::QVGPCI: - case PPC::ADDIStocHA: + case PPC::ADDIStocHA8: case PPC::ADDItocL: case PPC::LOAD_STACK_GUARD: case PPC::XXLXORz: diff --git a/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir index a46d21e3646..af5fb48b22d 100644 --- a/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir +++ b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir @@ -26,7 +26,7 @@ body: | bb.0: liveins: $x2 - %0:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @g_51 + %0:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @g_51 %1:g8rc_and_g8rc_nox0 = LDtocL @g_51, killed %0, implicit $x2 :: (load 8) %2:gprc = LI 0 %3:crrc = CMPLWI killed %2, 0 @@ -62,7 +62,7 @@ body: | # the full MIR like this. # # CHECK: bb.0: -# CHECK: %0:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @g_51 +# CHECK: %0:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @g_51 # CHECK-NEXT: %1:g8rc_and_g8rc_nox0 = LDtocL @g_51, killed %0, implicit killed $x2 :: (load 8) # CHECK-NEXT: %2:gprc = LI 0 # CHECK-NEXT: %3:crrc = CMPLWI killed %2, 0 diff --git a/test/CodeGen/PowerPC/aantidep-def-ec.mir b/test/CodeGen/PowerPC/aantidep-def-ec.mir index 7f224379c35..5ea1341f487 100644 --- a/test/CodeGen/PowerPC/aantidep-def-ec.mir +++ b/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -77,7 +77,7 @@ body: | $x30 = OR8 $x4, $x4 $x3 = LD 0, killed $x3 :: (load 8 from %ir.p1) $x29 = ADDI8 killed $x3, -48 - $x3 = ADDIStocHA $x2, @tasklist_lock + $x3 = ADDIStocHA8 $x2, @tasklist_lock $x3 = LDtocL @tasklist_lock, killed $x3, implicit $x2 :: (load 8 from got) BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3 $r3 = LI 0 diff --git a/test/CodeGen/PowerPC/licm-tocReg.ll b/test/CodeGen/PowerPC/licm-tocReg.ll index 82e44ef7b85..246bf7fbc20 100644 --- a/test/CodeGen/PowerPC/licm-tocReg.ll +++ b/test/CodeGen/PowerPC/licm-tocReg.ll @@ -1,6 +1,6 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; The instructions ADDIStocHA/LDtocL are used to calculate the address of +; The instructions ADDIStocHA8/LDtocL are used to calculate the address of ; globals. The ones that are in bb.3.if.end could not be hoisted by Machine ; LICM due to BCTRL_LDinto_toc in bb2.if.then. This call causes the compiler ; to insert a save TOC to stack before the call and load into X2 to restore TOC @@ -16,10 +16,10 @@ ; liveins: %x3 ; ; %4 = COPY %x3 -; %5 = ADDIStocHA %x2, @ga +; %5 = ADDIStocHA8 %x2, @ga ; %6 = LDtocL @ga, killed %5 :: (load 8 from got) ; %7 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga) -; %8 = ADDIStocHA %x2, @gb +; %8 = ADDIStocHA8 %x2, @gb ; %9 = LDtocL @gb, killed %8 :: (load 8 from got) ; %10 = LWZ 0, killed %9 :: (volatile dereferenceable load 4 from @gb) ; %0 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga) @@ -47,11 +47,11 @@ ; ; %2 = PHI %0, %bb.0.entry, %3, %bb.3.if.end ; %12 = ADDI %2, 1 -; %13 = ADDIStocHA %x2, @ga +; %13 = ADDIStocHA8 %x2, @ga ; %14 = LDtocL @ga, killed %13 :: (load 8 from got) ; STW killed %12, 0, %14 :: (volatile store 4 into @ga) ; %15 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga) -; %16 = ADDIStocHA %x2, @gb +; %16 = ADDIStocHA8 %x2, @gb ; %17 = LDtocL @gb, killed %16 :: (load 8 from got) ; %18 = LWZ 0, killed %17 :: (volatile dereferenceable load 4 from @gb) ; %3 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga) diff --git a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir index c43af3b0ca8..22aabf07c2f 100644 --- a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir +++ b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir @@ -70,7 +70,7 @@ body: | bb.0.entry: liveins: $x2 - %0 = ADDIStocHA $x2, @b + %0 = ADDIStocHA8 $x2, @b %1 = LD target-flags(ppc-toc-lo) @b, killed %0 :: (load 8 from @b) %2 = LWZ 0, %1 :: (load 4 from %ir.0) %3 = LI 0 diff --git a/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir b/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir index 7ede66c32e4..91694711604 100644 --- a/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir +++ b/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir @@ -110,7 +110,7 @@ body: | successors: %bb.5(0x30000000), %bb.1(0x50000000) liveins: $x2 - %3:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @b + %3:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @b %4:gprc = LWZ target-flags(ppc-toc-lo) @b, killed %3, implicit $x2 :: (dereferenceable load 4 from @b) %5:crrc = CMPLWI killed %4, 0 BCC 76, killed %5, %bb.5 @@ -120,16 +120,16 @@ body: | successors: %bb.2(0x80000000) liveins: $x2 - %6:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @d + %6:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @d %7:gprc = LWZ target-flags(ppc-toc-lo) @d, killed %6, implicit $x2 :: (dereferenceable load 4 from @d) %8:crrc = CMPWI killed %7, 0 %0:crbitrc = COPY killed %8.sub_eq %9:crbitrc = CRUNSET %19:gprc_and_gprc_nor0 = LI 0 %20:gprc_and_gprc_nor0 = LI 1 - %22:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @c - %10:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @e - %13:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @a + %22:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @c + %10:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @e + %13:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @a %14:g8rc_and_g8rc_nox0 = ADDItocL killed %13, @a, implicit $x2 bb.2.while.body: