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[X86] Add a DAG combines to turn vXi64 muls into VPMULDQ/VPMULUDQ if the upper bits are all sign bits or zeros.
Normally we catch this during lowering, but vXi64 mul is considered legal when we have AVX512DQ. This DAG combine allows us to avoid PMULLQ with AVX512DQ if we can prove its unnecessary. PMULLQ is 3 uops that take 4 cycles each. While pmuldq/pmuludq is only one 4 cycle uop. llvm-svn: 321437
This commit is contained in:
Craig Topper
parent
23389924ea
commit
242e8ec211
@ -32423,6 +32423,37 @@ static SDValue combineMulSpecial(uint64_t MulAmt, SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue combineVMUL(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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EVT VT = N->getValueType(0);
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SDLoc dl(N);
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if (VT.getScalarType() != MVT::i64)
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return SDValue();
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MVT MulVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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// MULDQ returns the 64-bit result of the signed multiplication of the lower
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// 32-bits. We can lower with this if the sign bits stretch that far.
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if (Subtarget.hasSSE41() && DAG.ComputeNumSignBits(LHS) > 32 &&
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DAG.ComputeNumSignBits(RHS) > 32) {
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return DAG.getNode(X86ISD::PMULDQ, dl, VT, DAG.getBitcast(MulVT, LHS),
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DAG.getBitcast(MulVT, RHS));
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}
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// If the upper bits are zero we can use a single pmuludq.
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APInt Mask = APInt::getHighBitsSet(64, 32);
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if (DAG.MaskedValueIsZero(LHS, Mask) && DAG.MaskedValueIsZero(RHS, Mask)) {
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return DAG.getNode(X86ISD::PMULUDQ, dl, VT, DAG.getBitcast(MulVT, LHS),
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DAG.getBitcast(MulVT, RHS));
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}
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return SDValue();
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}
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/// Optimize a single multiply with constant into two operations in order to
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/// implement it with two cheaper instructions, e.g. LEA + SHL, LEA + LEA.
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static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
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@ -32432,6 +32463,9 @@ static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
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if (DCI.isBeforeLegalize() && VT.isVector())
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return reduceVMULWidth(N, DAG, Subtarget);
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if (!DCI.isBeforeLegalize() && VT.isVector())
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return combineVMUL(N, DAG, Subtarget);
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if (!MulConstantOptimization)
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return SDValue();
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// An imul is usually smaller than the alternative sequence.
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@ -15,32 +15,14 @@ define <2 x i64> @combine_shuffle_sext_pmuldq(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-NEXT: pmuldq %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_shuffle_sext_pmuldq:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX2-NEXT: vpmovsxdq %xmm0, %xmm0
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; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; AVX2-NEXT: vpmovsxdq %xmm1, %xmm1
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; AVX2-NEXT: vpmuldq %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512VL-LABEL: combine_shuffle_sext_pmuldq:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX512VL-NEXT: vpmovsxdq %xmm0, %xmm0
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; AVX512VL-NEXT: vpmovsxdq %xmm1, %xmm1
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; AVX512VL-NEXT: vpmuldq %xmm1, %xmm0, %xmm0
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; AVX512VL-NEXT: retq
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;
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; AVX512DQVL-LABEL: combine_shuffle_sext_pmuldq:
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; AVX512DQVL: # %bb.0:
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; AVX512DQVL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX512DQVL-NEXT: vpmovsxdq %xmm0, %xmm0
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; AVX512DQVL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; AVX512DQVL-NEXT: vpmovsxdq %xmm1, %xmm1
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; AVX512DQVL-NEXT: vpmullq %xmm1, %xmm0, %xmm0
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; AVX512DQVL-NEXT: retq
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; AVX-LABEL: combine_shuffle_sext_pmuldq:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX-NEXT: vpmovsxdq %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; AVX-NEXT: vpmovsxdq %xmm1, %xmm1
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; AVX-NEXT: vpmuldq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
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%2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
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%3 = sext <2 x i32> %1 to <2 x i64>
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@ -60,32 +42,14 @@ define <2 x i64> @combine_shuffle_zext_pmuludq(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-NEXT: pmuludq %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_shuffle_zext_pmuludq:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512VL-LABEL: combine_shuffle_zext_pmuludq:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
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; AVX512VL-NEXT: retq
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;
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; AVX512DQVL-LABEL: combine_shuffle_zext_pmuludq:
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; AVX512DQVL: # %bb.0:
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; AVX512DQVL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX512DQVL-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX512DQVL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; AVX512DQVL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX512DQVL-NEXT: vpmullq %xmm1, %xmm0, %xmm0
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; AVX512DQVL-NEXT: retq
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; AVX-LABEL: combine_shuffle_zext_pmuludq:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
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%2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
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%3 = zext <2 x i32> %1 to <2 x i64>
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@ -497,7 +497,7 @@ define <8 x i32> @test9(%struct.ST* %base, <8 x i64> %ind1, <8 x i32>%ind5) {
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; SKX_SMALL-NEXT: vpbroadcastq %rdi, %zmm2
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; SKX_SMALL-NEXT: vpmullq {{.*}}(%rip){1to8}, %zmm0, %zmm0
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; SKX_SMALL-NEXT: vpmovsxdq %ymm1, %zmm1
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; SKX_SMALL-NEXT: vpmullq {{.*}}(%rip){1to8}, %zmm1, %zmm1
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; SKX_SMALL-NEXT: vpmuldq {{.*}}(%rip){1to8}, %zmm1, %zmm1
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; SKX_SMALL-NEXT: vpaddq %zmm1, %zmm0, %zmm0
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; SKX_SMALL-NEXT: vpaddq %zmm0, %zmm2, %zmm0
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; SKX_SMALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1
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@ -510,7 +510,7 @@ define <8 x i32> @test9(%struct.ST* %base, <8 x i64> %ind1, <8 x i32>%ind5) {
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; SKX_LARGE-NEXT: vpbroadcastq %rdi, %zmm2
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; SKX_LARGE-NEXT: vpmovsxdq %ymm1, %zmm1
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; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax
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; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm1, %zmm1
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; SKX_LARGE-NEXT: vpmuldq (%rax){1to8}, %zmm1, %zmm1
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; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax
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; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm0, %zmm0
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; SKX_LARGE-NEXT: vpaddq %zmm1, %zmm0, %zmm0
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@ -582,7 +582,7 @@ define <8 x i32> @test10(%struct.ST* %base, <8 x i64> %i1, <8 x i32>%ind5) {
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; SKX_SMALL-NEXT: vpbroadcastq %rdi, %zmm2
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; SKX_SMALL-NEXT: vpmullq {{.*}}(%rip){1to8}, %zmm0, %zmm0
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; SKX_SMALL-NEXT: vpmovsxdq %ymm1, %zmm1
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; SKX_SMALL-NEXT: vpmullq {{.*}}(%rip){1to8}, %zmm1, %zmm1
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; SKX_SMALL-NEXT: vpmuldq {{.*}}(%rip){1to8}, %zmm1, %zmm1
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; SKX_SMALL-NEXT: vpaddq %zmm1, %zmm0, %zmm0
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; SKX_SMALL-NEXT: vpaddq %zmm0, %zmm2, %zmm0
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; SKX_SMALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1
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@ -595,7 +595,7 @@ define <8 x i32> @test10(%struct.ST* %base, <8 x i64> %i1, <8 x i32>%ind5) {
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; SKX_LARGE-NEXT: vpbroadcastq %rdi, %zmm2
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; SKX_LARGE-NEXT: vpmovsxdq %ymm1, %zmm1
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; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax
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; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm1, %zmm1
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; SKX_LARGE-NEXT: vpmuldq (%rax){1to8}, %zmm1, %zmm1
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; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax
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; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm0, %zmm0
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; SKX_LARGE-NEXT: vpaddq %zmm1, %zmm0, %zmm0
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