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[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test
llvm-svn: 354028
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c2a2194aef
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@ -1,6 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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@gi = external global i32
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@ -13,6 +15,15 @@ define i32 @constraint_r(i32 %a) {
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_r:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, %hi(gi)
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; RV64I-NEXT: lwu a1, %lo(gi)(a1)
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = load i32, i32* @gi
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%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
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ret i32 %2
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@ -25,6 +36,13 @@ define i32 @constraint_i(i32 %a) {
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; RV32I-NEXT: addi a0, a0, 113
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_i:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, 113
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = load i32, i32* @gi
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%2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
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ret i32 %2
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@ -36,6 +54,12 @@ define void @constraint_m(i32* %a) {
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; RV32I-NEXT: #APP
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_m:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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call void asm sideeffect "", "=*m"(i32* %a)
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ret void
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}
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@ -47,6 +71,13 @@ define i32 @constraint_m2(i32* %a) {
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_m2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind
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ret i32 %1
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}
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