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[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test

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llvm-svn: 354028
This commit is contained in:
Alex Bradbury 2019-02-14 13:09:54 +00:00
parent c2a2194aef
commit 245a68cf04
1 changed files with 31 additions and 0 deletions
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31
test/CodeGen/RISCV/inline-asm.ll
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@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
@gi = external global i32 @gi = external global i32
@ -13,6 +15,15 @@ define i32 @constraint_r(i32 %a) {
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
;
; RV64I-LABEL: constraint_r:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, %hi(gi)
; RV64I-NEXT: lwu a1, %lo(gi)(a1)
; RV64I-NEXT: #APP
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret
%1 = load i32, i32* @gi %1 = load i32, i32* @gi
%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1) %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
ret i32 %2 ret i32 %2
@ -25,6 +36,13 @@ define i32 @constraint_i(i32 %a) {
; RV32I-NEXT: addi a0, a0, 113 ; RV32I-NEXT: addi a0, a0, 113
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
;
; RV64I-LABEL: constraint_i:
; RV64I: # %bb.0:
; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a0, 113
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret
%1 = load i32, i32* @gi %1 = load i32, i32* @gi
%2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113) %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
ret i32 %2 ret i32 %2
@ -36,6 +54,12 @@ define void @constraint_m(i32* %a) {
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
;
; RV64I-LABEL: constraint_m:
; RV64I: # %bb.0:
; RV64I-NEXT: #APP
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret
call void asm sideeffect "", "=*m"(i32* %a) call void asm sideeffect "", "=*m"(i32* %a)
ret void ret void
} }
@ -47,6 +71,13 @@ define i32 @constraint_m2(i32* %a) {
; RV32I-NEXT: lw a0, 0(a0) ; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
;
; RV64I-LABEL: constraint_m2:
; RV64I: # %bb.0:
; RV64I-NEXT: #APP
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret
%1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind %1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind
ret i32 %1 ret i32 %1
} }