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[PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

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This patch implements the vec_expandm function prototypes in altivec.h in order
to utilize the vector expand with mask instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82727
This commit is contained in:
Amy Kwan 2020-09-03 12:33:53 -05:00
parent 99a542ef5d
commit 2477050bd8
3 changed files with 78 additions and 5 deletions
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12
include/llvm/IR/IntrinsicsPowerPC.td
View File

@ -455,6 +455,18 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
def int_ppc_altivec_vextractqm : GCCBuiltin<"__builtin_altivec_vextractqm">,
Intrinsic<[llvm_i32_ty], [llvm_v1i128_ty], [IntrNoMem]>;
// P10 Vector Expand with Mask
def int_ppc_altivec_vexpandbm : GCCBuiltin<"__builtin_altivec_vexpandbm">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_ppc_altivec_vexpandhm : GCCBuiltin<"__builtin_altivec_vexpandhm">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_ppc_altivec_vexpandwm : GCCBuiltin<"__builtin_altivec_vexpandwm">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
def int_ppc_altivec_vexpanddm : GCCBuiltin<"__builtin_altivec_vexpanddm">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
def int_ppc_altivec_vexpandqm : GCCBuiltin<"__builtin_altivec_vexpandqm">,
Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty], [IntrNoMem]>;
// P10 Vector Parallel Bits Deposit/Extract Doubleword Builtins.
def int_ppc_altivec_vpdepd : GCCBuiltin<"__builtin_altivec_vpdepd">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],

15
lib/Target/PowerPC/PPCInstrPrefix.td
View File

@ -1003,19 +1003,24 @@ let Predicates = [IsISA3_1] in {
(int_ppc_altivec_vextractqm v1i128:$vB))]>;
def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB),
"vexpandbm $vD, $vB", IIC_VecGeneral,
[]>;
[(set v16i8:$vD, (int_ppc_altivec_vexpandbm
v16i8:$vB))]>;
def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB),
"vexpandhm $vD, $vB", IIC_VecGeneral,
[]>;
[(set v8i16:$vD, (int_ppc_altivec_vexpandhm
v8i16:$vB))]>;
def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB),
"vexpandwm $vD, $vB", IIC_VecGeneral,
[]>;
[(set v4i32:$vD, (int_ppc_altivec_vexpandwm
v4i32:$vB))]>;
def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB),
"vexpanddm $vD, $vB", IIC_VecGeneral,
[]>;
[(set v2i64:$vD, (int_ppc_altivec_vexpanddm
v2i64:$vB))]>;
def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB),
"vexpandqm $vD, $vB", IIC_VecGeneral,
[]>;
[(set v1i128:$vD, (int_ppc_altivec_vexpandqm
v1i128:$vB))]>;
def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB),
"mtvsrbm $vD, $rB", IIC_VecGeneral,
[]>;

56
test/CodeGen/PowerPC/p10-vector-mask-ops.ll
View File

@ -64,3 +64,59 @@ entry:
%ext = tail call i32 @llvm.ppc.altivec.vextractqm(<1 x i128> %a)
ret i32 %ext
}
declare <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8>)
declare <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16>)
declare <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32>)
declare <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64>)
declare <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128>)
define <16 x i8> @test_vexpandbm(<16 x i8> %a) {
; CHECK-LABEL: test_vexpandbm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vexpandbm v2, v2
; CHECK-NEXT: blr
entry:
%exp = tail call <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8> %a)
ret <16 x i8> %exp
}
define <8 x i16> @test_vexpandhm(<8 x i16> %a) {
; CHECK-LABEL: test_vexpandhm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vexpandhm v2, v2
; CHECK-NEXT: blr
entry:
%exp = tail call <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16> %a)
ret <8 x i16> %exp
}
define <4 x i32> @test_vexpandwm(<4 x i32> %a) {
; CHECK-LABEL: test_vexpandwm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vexpandwm v2, v2
; CHECK-NEXT: blr
entry:
%exp = tail call <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32> %a)
ret <4 x i32> %exp
}
define <2 x i64> @test_vexpanddm(<2 x i64> %a) {
; CHECK-LABEL: test_vexpanddm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vexpanddm v2, v2
; CHECK-NEXT: blr
entry:
%exp = tail call <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64> %a)
ret <2 x i64> %exp
}
define <1 x i128> @test_vexpandqm(<1 x i128> %a) {
; CHECK-LABEL: test_vexpandqm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vexpandqm v2, v2
; CHECK-NEXT: blr
entry:
%exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a)
ret <1 x i128> %exp
}