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Check all patterns for missing instruction flags.
Both single-instruction and multi-instruction patterns can be checked for missing mayLoad / mayStore, and hasSideEffects flags. llvm-svn: 162734
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@ -2027,6 +2027,9 @@ CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R) :
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// stores, and side effects in many cases by examining an
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// instruction's pattern.
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InferInstructionFlags();
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// Verify that instruction flags match the patterns.
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VerifyInstructionFlags();
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}
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CodeGenDAGPatterns::~CodeGenDAGPatterns() {
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@ -2405,6 +2408,7 @@ private:
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return OpInfo.getEnumName() == "ISD::BITCAST";
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}
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public:
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void AnalyzeNode(const TreePatternNode *N) {
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if (N->isLeaf()) {
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if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
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@ -2937,6 +2941,73 @@ void CodeGenDAGPatterns::InferInstructionFlags() {
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}
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}
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/// Verify instruction flags against pattern node properties.
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void CodeGenDAGPatterns::VerifyInstructionFlags() {
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unsigned Errors = 0;
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for (ptm_iterator I = ptm_begin(), E = ptm_end(); I != E; ++I) {
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const PatternToMatch &PTM = *I;
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SmallVector<Record*, 8> Instrs;
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getInstructionsInTree(PTM.getDstPattern(), Instrs);
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if (Instrs.empty())
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continue;
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// Count the number of instructions with each flag set.
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unsigned NumSideEffects = 0;
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unsigned NumStores = 0;
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unsigned NumLoads = 0;
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for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
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const CodeGenInstruction &InstInfo = Target.getInstruction(Instrs[i]);
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NumSideEffects += InstInfo.hasSideEffects;
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NumStores += InstInfo.mayStore;
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NumLoads += InstInfo.mayLoad;
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}
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// Analyze the source pattern.
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InstAnalyzer PatInfo(*this);
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PatInfo.Analyze(&PTM);
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// Collect error messages.
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SmallVector<std::string, 4> Msgs;
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// Check for missing flags in the output.
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// Permit extra flags for now at least.
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if (PatInfo.hasSideEffects && !NumSideEffects)
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Msgs.push_back("pattern has side effects, but hasSideEffects isn't set");
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// Don't verify store flags on instructions with side effects. At least for
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// intrinsics, side effects implies mayStore.
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if (!PatInfo.hasSideEffects && PatInfo.mayStore && !NumStores)
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Msgs.push_back("pattern may store, but mayStore isn't set");
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// Similarly, mayStore implies mayLoad on intrinsics.
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if (!PatInfo.mayStore && PatInfo.mayLoad && !NumLoads)
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Msgs.push_back("pattern may load, but mayLoad isn't set");
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// Print error messages.
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if (Msgs.empty())
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continue;
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++Errors;
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for (unsigned i = 0, e = Msgs.size(); i != e; ++i)
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PrintError(PTM.getSrcRecord()->getLoc(), Twine(Msgs[i]) + " on the " +
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(Instrs.size() == 1 ?
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"instruction" : "output instructions"));
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// Provide the location of the relevant instruction definitions.
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for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
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if (Instrs[i] != PTM.getSrcRecord())
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PrintError(Instrs[i]->getLoc(), "defined here");
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const CodeGenInstruction &InstInfo = Target.getInstruction(Instrs[i]);
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if (InstInfo.InferredFrom &&
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InstInfo.InferredFrom != InstInfo.TheDef &&
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InstInfo.InferredFrom != PTM.getSrcRecord())
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PrintError(InstInfo.InferredFrom->getLoc(), "inferred from patttern");
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}
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}
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if (Errors)
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throw "Errors in DAG patterns";
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}
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/// Given a pattern result with an unresolved type, see if we can find one
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/// instruction with an unresolved result type. Force this result type to an
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/// arbitrary element if it's possible types to converge results.
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@ -797,6 +797,7 @@ private:
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void ParsePatterns();
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void InferInstructionFlags();
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void GenerateVariants();
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void VerifyInstructionFlags();
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void AddPatternToMatch(const TreePattern *Pattern, const PatternToMatch &PTM);
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void FindPatternInputsAndOutputs(TreePattern *I, TreePatternNode *Pat,
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