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https://github.com/RPCS3/llvm-mirror.git
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Fix line-endings, NFC
A follow-up commit is adding a RUN line to each of these tests, so fix the line endings first. This is a whitespace-only change. llvm-svn: 214156
This commit is contained in:
Duncan P. N. Exon Smith
parent
4936d185e0
commit
2512622ff7
@ -1,33 +1,33 @@
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; RUN: llvm-dis < %s.bc| FileCheck %s
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; aggregateOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
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; The test checks that LLVM does not misread instructions with aggregate operands
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; in older bitcode files.
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define void @extractvalue([4 x i8] %x1, [4 x [4 x i8]] %x2, {{i32, float}} %x3){
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entry:
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; CHECK: %res1 = extractvalue [4 x i8] %x1, 0
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%res1 = extractvalue [4 x i8] %x1, 0
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; CHECK-NEXT: %res2 = extractvalue [4 x [4 x i8]] %x2, 1
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%res2 = extractvalue [4 x [4 x i8 ]] %x2, 1
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; CHECK-NEXT: %res3 = extractvalue [4 x [4 x i8]] %x2, 0, 1
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%res3 = extractvalue [4 x [4 x i8 ]] %x2, 0, 1
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; CHECK-NEXT: %res4 = extractvalue { { i32, float } } %x3, 0, 1
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%res4 = extractvalue {{i32, float}} %x3, 0, 1
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ret void
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}
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define void @insertvalue([4 x [4 x i8 ]] %x1){
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entry:
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; CHECK: %res1 = insertvalue [4 x [4 x i8]] %x1, i8 0, 0, 0
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%res1 = insertvalue [4 x [4 x i8 ]] %x1, i8 0, 0, 0
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; CHECK-NEXT: %res2 = insertvalue [4 x [4 x i8]] undef, i8 0, 0, 0
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%res2 = insertvalue [4 x [4 x i8 ]] undef, i8 0, 0, 0
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ret void
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}
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; RUN: llvm-dis < %s.bc| FileCheck %s
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; aggregateOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
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; The test checks that LLVM does not misread instructions with aggregate operands
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; in older bitcode files.
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define void @extractvalue([4 x i8] %x1, [4 x [4 x i8]] %x2, {{i32, float}} %x3){
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entry:
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; CHECK: %res1 = extractvalue [4 x i8] %x1, 0
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%res1 = extractvalue [4 x i8] %x1, 0
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; CHECK-NEXT: %res2 = extractvalue [4 x [4 x i8]] %x2, 1
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%res2 = extractvalue [4 x [4 x i8 ]] %x2, 1
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; CHECK-NEXT: %res3 = extractvalue [4 x [4 x i8]] %x2, 0, 1
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%res3 = extractvalue [4 x [4 x i8 ]] %x2, 0, 1
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; CHECK-NEXT: %res4 = extractvalue { { i32, float } } %x3, 0, 1
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%res4 = extractvalue {{i32, float}} %x3, 0, 1
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ret void
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}
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define void @insertvalue([4 x [4 x i8 ]] %x1){
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entry:
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; CHECK: %res1 = insertvalue [4 x [4 x i8]] %x1, i8 0, 0, 0
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%res1 = insertvalue [4 x [4 x i8 ]] %x1, i8 0, 0, 0
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; CHECK-NEXT: %res2 = insertvalue [4 x [4 x i8]] undef, i8 0, 0, 0
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%res2 = insertvalue [4 x [4 x i8 ]] undef, i8 0, 0, 0
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ret void
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}
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@ -14,4 +14,4 @@ define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
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; CHECK: cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new singlethread release monotonic
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ret void
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}
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}
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@ -1,120 +1,120 @@
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; RUN: llvm-dis < %s.bc| FileCheck %s
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; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
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; The test checks that LLVM does not misread binary float instructions from
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; older bitcode files.
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define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
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entry:
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; CHECK: %res1 = fadd float %x1, %x1
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%res1 = fadd float %x1, %x1
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; CHECK-NEXT: %res2 = fadd double %x2, %x2
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%res2 = fadd double %x2, %x2
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; CHECK-NEXT: %res3 = fadd half %x3, %x3
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%res3 = fadd half %x3, %x3
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; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4
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%res4 = fadd fp128 %x4, %x4
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; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5
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%res5 = fadd x86_fp80 %x5, %x5
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; CHECK-NEXT: %res6 = fadd ppc_fp128 %x6, %x6
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%res6 = fadd ppc_fp128 %x6, %x6
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ret void
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}
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define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){
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entry:
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; CHECK: %res1 = fadd <2 x float> %x1, %x1
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%res1 = fadd <2 x float> %x1, %x1
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; CHECK-NEXT: %res2 = fadd <3 x float> %x2, %x2
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%res2 = fadd <3 x float> %x2, %x2
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; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3
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%res3 = fadd <4 x float> %x3, %x3
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; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4
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%res4 = fadd <8 x float> %x4, %x4
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; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5
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%res5 = fadd <16 x float> %x5, %x5
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ret void
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}
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define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){
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entry:
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; CHECK: %res1 = fadd <2 x double> %x1, %x1
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%res1 = fadd <2 x double> %x1, %x1
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; CHECK-NEXT: %res2 = fadd <3 x double> %x2, %x2
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%res2 = fadd <3 x double> %x2, %x2
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; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3
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%res3 = fadd <4 x double> %x3, %x3
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; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4
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%res4 = fadd <8 x double> %x4, %x4
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; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5
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%res5 = fadd <16 x double> %x5, %x5
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ret void
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}
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define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){
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entry:
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; CHECK: %res1 = fadd <2 x half> %x1, %x1
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%res1 = fadd <2 x half> %x1, %x1
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; CHECK-NEXT: %res2 = fadd <3 x half> %x2, %x2
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%res2 = fadd <3 x half> %x2, %x2
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; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3
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%res3 = fadd <4 x half> %x3, %x3
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; CHECK-NEXT: %res4 = fadd <8 x half> %x4, %x4
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%res4 = fadd <8 x half> %x4, %x4
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; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5
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%res5 = fadd <16 x half> %x5, %x5
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ret void
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}
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define void @fsub(float %x1){
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entry:
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; CHECK: %res1 = fsub float %x1, %x1
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%res1 = fsub float %x1, %x1
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ret void
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}
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define void @fmul(float %x1){
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entry:
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; CHECK: %res1 = fmul float %x1, %x1
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%res1 = fmul float %x1, %x1
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ret void
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}
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define void @fdiv(float %x1){
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entry:
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; CHECK: %res1 = fdiv float %x1, %x1
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%res1 = fdiv float %x1, %x1
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ret void
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}
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define void @frem(float %x1){
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entry:
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; CHECK: %res1 = frem float %x1, %x1
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%res1 = frem float %x1, %x1
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ret void
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}
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; RUN: llvm-dis < %s.bc| FileCheck %s
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; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
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; The test checks that LLVM does not misread binary float instructions from
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; older bitcode files.
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define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
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entry:
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; CHECK: %res1 = fadd float %x1, %x1
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%res1 = fadd float %x1, %x1
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; CHECK-NEXT: %res2 = fadd double %x2, %x2
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%res2 = fadd double %x2, %x2
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; CHECK-NEXT: %res3 = fadd half %x3, %x3
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%res3 = fadd half %x3, %x3
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; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4
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%res4 = fadd fp128 %x4, %x4
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; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5
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%res5 = fadd x86_fp80 %x5, %x5
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; CHECK-NEXT: %res6 = fadd ppc_fp128 %x6, %x6
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%res6 = fadd ppc_fp128 %x6, %x6
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ret void
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}
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define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){
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entry:
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; CHECK: %res1 = fadd <2 x float> %x1, %x1
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%res1 = fadd <2 x float> %x1, %x1
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; CHECK-NEXT: %res2 = fadd <3 x float> %x2, %x2
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%res2 = fadd <3 x float> %x2, %x2
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; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3
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%res3 = fadd <4 x float> %x3, %x3
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; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4
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%res4 = fadd <8 x float> %x4, %x4
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; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5
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%res5 = fadd <16 x float> %x5, %x5
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ret void
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}
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define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){
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entry:
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; CHECK: %res1 = fadd <2 x double> %x1, %x1
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%res1 = fadd <2 x double> %x1, %x1
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; CHECK-NEXT: %res2 = fadd <3 x double> %x2, %x2
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%res2 = fadd <3 x double> %x2, %x2
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; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3
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%res3 = fadd <4 x double> %x3, %x3
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; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4
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%res4 = fadd <8 x double> %x4, %x4
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; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5
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%res5 = fadd <16 x double> %x5, %x5
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ret void
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}
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define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){
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entry:
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; CHECK: %res1 = fadd <2 x half> %x1, %x1
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%res1 = fadd <2 x half> %x1, %x1
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; CHECK-NEXT: %res2 = fadd <3 x half> %x2, %x2
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%res2 = fadd <3 x half> %x2, %x2
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; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3
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%res3 = fadd <4 x half> %x3, %x3
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; CHECK-NEXT: %res4 = fadd <8 x half> %x4, %x4
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%res4 = fadd <8 x half> %x4, %x4
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; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5
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%res5 = fadd <16 x half> %x5, %x5
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ret void
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}
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define void @fsub(float %x1){
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entry:
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; CHECK: %res1 = fsub float %x1, %x1
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%res1 = fsub float %x1, %x1
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ret void
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}
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define void @fmul(float %x1){
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entry:
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; CHECK: %res1 = fmul float %x1, %x1
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%res1 = fmul float %x1, %x1
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ret void
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}
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define void @fdiv(float %x1){
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entry:
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; CHECK: %res1 = fdiv float %x1, %x1
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%res1 = fdiv float %x1, %x1
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ret void
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}
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define void @frem(float %x1){
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entry:
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; CHECK: %res1 = frem float %x1, %x1
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%res1 = frem float %x1, %x1
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ret void
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}
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@ -1,177 +1,177 @@
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; RUN: llvm-dis < %s.bc| FileCheck %s
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; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
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; The test checks that LLVM does not misread binary integer instructions from
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; older bitcode files.
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define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
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entry:
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; CHECK: %res1 = add i1 %x1, %x1
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%res1 = add i1 %x1, %x1
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; CHECK-NEXT: %res2 = add i8 %x2, %x2
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%res2 = add i8 %x2, %x2
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; CHECK-NEXT: %res3 = add i16 %x3, %x3
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%res3 = add i16 %x3, %x3
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; CHECK-NEXT: %res4 = add i32 %x4, %x4
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%res4 = add i32 %x4, %x4
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; CHECK-NEXT: %res5 = add i64 %x5, %x5
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%res5 = add i64 %x5, %x5
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; CHECK: %res6 = add nuw i1 %x1, %x1
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%res6 = add nuw i1 %x1, %x1
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; CHECK: %res7 = add nsw i1 %x1, %x1
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%res7 = add nsw i1 %x1, %x1
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; CHECK: %res8 = add nuw nsw i1 %x1, %x1
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%res8 = add nuw nsw i1 %x1, %x1
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ret void
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}
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define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
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entry:
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; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1
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%res1 = add nuw nsw <2 x i8> %x1, %x1
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; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2
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%res2 = add nuw nsw <3 x i8> %x2, %x2
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; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3
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%res3 = add nuw nsw <4 x i8> %x3, %x3
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; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4
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%res4 = add nuw nsw <8 x i8> %x4, %x4
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; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5
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%res5 = add nuw nsw <16 x i8> %x5, %x5
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ret void
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}
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define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){
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entry:
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; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1
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%res1 = add nuw nsw <2 x i16> %x1, %x1
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; CHECK-NEXT: %res2 = add nuw nsw <3 x i16> %x2, %x2
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%res2 = add nuw nsw <3 x i16> %x2, %x2
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; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3
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%res3 = add nuw nsw <4 x i16> %x3, %x3
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; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4
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%res4 = add nuw nsw <8 x i16> %x4, %x4
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; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5
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%res5 = add nuw nsw <16 x i16> %x5, %x5
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ret void
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}
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define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){
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entry:
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; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1
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%res1 = add nuw nsw <2 x i32> %x1, %x1
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; CHECK-NEXT: %res2 = add nuw nsw <3 x i32> %x2, %x2
|
||||
%res2 = add nuw nsw <3 x i32> %x2, %x2
|
||||
|
||||
; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3
|
||||
%res3 = add nuw nsw <4 x i32> %x3, %x3
|
||||
|
||||
; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x4
|
||||
%res4 = add nuw nsw <8 x i32> %x4, %x4
|
||||
|
||||
; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5
|
||||
%res5 = add nuw nsw <16 x i32> %x5, %x5
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @addvec64NuwNsw(<2 x i64> %x1, <3 x i64> %x2 ,<4 x i64> %x3, <8 x i64> %x4, <16 x i64> %x5){
|
||||
entry:
|
||||
; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1
|
||||
%res1 = add nuw nsw <2 x i64> %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = add nuw nsw <3 x i64> %x2, %x2
|
||||
%res2 = add nuw nsw <3 x i64> %x2, %x2
|
||||
|
||||
; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3
|
||||
%res3 = add nuw nsw <4 x i64> %x3, %x3
|
||||
|
||||
; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4
|
||||
%res4 = add nuw nsw <8 x i64> %x4, %x4
|
||||
|
||||
; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5
|
||||
%res5 = add nuw nsw <16 x i64> %x5, %x5
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sub(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = sub i8 %x1, %x1
|
||||
%res1 = sub i8 %x1, %x1
|
||||
|
||||
; CHECK: %res2 = sub nuw i8 %x1, %x1
|
||||
%res2 = sub nuw i8 %x1, %x1
|
||||
|
||||
; CHECK: %res3 = sub nsw i8 %x1, %x1
|
||||
%res3 = sub nsw i8 %x1, %x1
|
||||
|
||||
; CHECK: %res4 = sub nuw nsw i8 %x1, %x1
|
||||
%res4 = sub nuw nsw i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @mul(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = mul i8 %x1, %x1
|
||||
%res1 = mul i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @udiv(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = udiv i8 %x1, %x1
|
||||
%res1 = udiv i8 %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1
|
||||
%res2 = udiv exact i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sdiv(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = sdiv i8 %x1, %x1
|
||||
%res1 = sdiv i8 %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1
|
||||
%res2 = sdiv exact i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @urem(i32 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = urem i32 %x1, %x1
|
||||
%res1 = urem i32 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @srem(i32 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = srem i32 %x1, %x1
|
||||
%res1 = srem i32 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread binary integer instructions from
|
||||
; older bitcode files.
|
||||
|
||||
define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
|
||||
entry:
|
||||
; CHECK: %res1 = add i1 %x1, %x1
|
||||
%res1 = add i1 %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = add i8 %x2, %x2
|
||||
%res2 = add i8 %x2, %x2
|
||||
|
||||
; CHECK-NEXT: %res3 = add i16 %x3, %x3
|
||||
%res3 = add i16 %x3, %x3
|
||||
|
||||
; CHECK-NEXT: %res4 = add i32 %x4, %x4
|
||||
%res4 = add i32 %x4, %x4
|
||||
|
||||
; CHECK-NEXT: %res5 = add i64 %x5, %x5
|
||||
%res5 = add i64 %x5, %x5
|
||||
|
||||
; CHECK: %res6 = add nuw i1 %x1, %x1
|
||||
%res6 = add nuw i1 %x1, %x1
|
||||
|
||||
; CHECK: %res7 = add nsw i1 %x1, %x1
|
||||
%res7 = add nsw i1 %x1, %x1
|
||||
|
||||
; CHECK: %res8 = add nuw nsw i1 %x1, %x1
|
||||
%res8 = add nuw nsw i1 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
|
||||
entry:
|
||||
; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1
|
||||
%res1 = add nuw nsw <2 x i8> %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2
|
||||
%res2 = add nuw nsw <3 x i8> %x2, %x2
|
||||
|
||||
; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3
|
||||
%res3 = add nuw nsw <4 x i8> %x3, %x3
|
||||
|
||||
; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4
|
||||
%res4 = add nuw nsw <8 x i8> %x4, %x4
|
||||
|
||||
; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5
|
||||
%res5 = add nuw nsw <16 x i8> %x5, %x5
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){
|
||||
entry:
|
||||
; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1
|
||||
%res1 = add nuw nsw <2 x i16> %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = add nuw nsw <3 x i16> %x2, %x2
|
||||
%res2 = add nuw nsw <3 x i16> %x2, %x2
|
||||
|
||||
; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3
|
||||
%res3 = add nuw nsw <4 x i16> %x3, %x3
|
||||
|
||||
; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4
|
||||
%res4 = add nuw nsw <8 x i16> %x4, %x4
|
||||
|
||||
; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5
|
||||
%res5 = add nuw nsw <16 x i16> %x5, %x5
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){
|
||||
entry:
|
||||
; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1
|
||||
%res1 = add nuw nsw <2 x i32> %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = add nuw nsw <3 x i32> %x2, %x2
|
||||
%res2 = add nuw nsw <3 x i32> %x2, %x2
|
||||
|
||||
; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3
|
||||
%res3 = add nuw nsw <4 x i32> %x3, %x3
|
||||
|
||||
; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x4
|
||||
%res4 = add nuw nsw <8 x i32> %x4, %x4
|
||||
|
||||
; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5
|
||||
%res5 = add nuw nsw <16 x i32> %x5, %x5
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @addvec64NuwNsw(<2 x i64> %x1, <3 x i64> %x2 ,<4 x i64> %x3, <8 x i64> %x4, <16 x i64> %x5){
|
||||
entry:
|
||||
; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1
|
||||
%res1 = add nuw nsw <2 x i64> %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = add nuw nsw <3 x i64> %x2, %x2
|
||||
%res2 = add nuw nsw <3 x i64> %x2, %x2
|
||||
|
||||
; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3
|
||||
%res3 = add nuw nsw <4 x i64> %x3, %x3
|
||||
|
||||
; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4
|
||||
%res4 = add nuw nsw <8 x i64> %x4, %x4
|
||||
|
||||
; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5
|
||||
%res5 = add nuw nsw <16 x i64> %x5, %x5
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sub(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = sub i8 %x1, %x1
|
||||
%res1 = sub i8 %x1, %x1
|
||||
|
||||
; CHECK: %res2 = sub nuw i8 %x1, %x1
|
||||
%res2 = sub nuw i8 %x1, %x1
|
||||
|
||||
; CHECK: %res3 = sub nsw i8 %x1, %x1
|
||||
%res3 = sub nsw i8 %x1, %x1
|
||||
|
||||
; CHECK: %res4 = sub nuw nsw i8 %x1, %x1
|
||||
%res4 = sub nuw nsw i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @mul(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = mul i8 %x1, %x1
|
||||
%res1 = mul i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @udiv(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = udiv i8 %x1, %x1
|
||||
%res1 = udiv i8 %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1
|
||||
%res2 = udiv exact i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sdiv(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = sdiv i8 %x1, %x1
|
||||
%res1 = sdiv i8 %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1
|
||||
%res2 = sdiv exact i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @urem(i32 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = urem i32 %x1, %x1
|
||||
%res1 = urem i32 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @srem(i32 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = srem i32 %x1, %x1
|
||||
%res1 = srem i32 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,68 +1,68 @@
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; bitwiseOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread bitwise instructions from
|
||||
; older bitcode files.
|
||||
|
||||
define void @shl(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = shl i8 %x1, %x1
|
||||
%res1 = shl i8 %x1, %x1
|
||||
|
||||
; CHECK: %res2 = shl nuw i8 %x1, %x1
|
||||
%res2 = shl nuw i8 %x1, %x1
|
||||
|
||||
; CHECK: %res3 = shl nsw i8 %x1, %x1
|
||||
%res3 = shl nsw i8 %x1, %x1
|
||||
|
||||
; CHECK: %res4 = shl nuw nsw i8 %x1, %x1
|
||||
%res4 = shl nuw nsw i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @lshr(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = lshr i8 %x1, %x1
|
||||
%res1 = lshr i8 %x1, %x1
|
||||
|
||||
; CHECK: %res2 = lshr exact i8 %x1, %x1
|
||||
%res2 = lshr exact i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @ashr(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = ashr i8 %x1, %x1
|
||||
%res1 = ashr i8 %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = ashr exact i8 %x1, %x1
|
||||
%res2 = ashr exact i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @and(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = and i8 %x1, %x1
|
||||
%res1 = and i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @or(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = or i8 %x1, %x1
|
||||
%res1 = or i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @xor(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = xor i8 %x1, %x1
|
||||
%res1 = xor i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; bitwiseOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread bitwise instructions from
|
||||
; older bitcode files.
|
||||
|
||||
define void @shl(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = shl i8 %x1, %x1
|
||||
%res1 = shl i8 %x1, %x1
|
||||
|
||||
; CHECK: %res2 = shl nuw i8 %x1, %x1
|
||||
%res2 = shl nuw i8 %x1, %x1
|
||||
|
||||
; CHECK: %res3 = shl nsw i8 %x1, %x1
|
||||
%res3 = shl nsw i8 %x1, %x1
|
||||
|
||||
; CHECK: %res4 = shl nuw nsw i8 %x1, %x1
|
||||
%res4 = shl nuw nsw i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @lshr(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = lshr i8 %x1, %x1
|
||||
%res1 = lshr i8 %x1, %x1
|
||||
|
||||
; CHECK: %res2 = lshr exact i8 %x1, %x1
|
||||
%res2 = lshr exact i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @ashr(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = ashr i8 %x1, %x1
|
||||
%res1 = ashr i8 %x1, %x1
|
||||
|
||||
; CHECK-NEXT: %res2 = ashr exact i8 %x1, %x1
|
||||
%res2 = ashr exact i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @and(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = and i8 %x1, %x1
|
||||
%res1 = and i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @or(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = or i8 %x1, %x1
|
||||
%res1 = or i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @xor(i8 %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = xor i8 %x1, %x1
|
||||
%res1 = xor i8 %x1, %x1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -20,4 +20,4 @@ define void @test(i32* %addr) {
|
||||
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 seq_cst seq_cst
|
||||
|
||||
ret void
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,104 +1,104 @@
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; conversionOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread conversion instructions from
|
||||
; older bitcode files.
|
||||
|
||||
define void @trunc(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = trunc i32 %src to i8
|
||||
%res1 = trunc i32 %src to i8
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @zext(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = zext i32 %src to i64
|
||||
%res1 = zext i32 %src to i64
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sext(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = sext i32 %src to i64
|
||||
%res1 = sext i32 %src to i64
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptrunc(double %src){
|
||||
entry:
|
||||
; CHECK: %res1 = fptrunc double %src to float
|
||||
%res1 = fptrunc double %src to float
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fpext(float %src){
|
||||
entry:
|
||||
; CHECK: %res1 = fpext float %src to double
|
||||
%res1 = fpext float %src to double
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptoui(float %src){
|
||||
entry:
|
||||
; CHECK: %res1 = fptoui float %src to i32
|
||||
%res1 = fptoui float %src to i32
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptosi(float %src){
|
||||
entry:
|
||||
; CHECK: %res1 = fptosi float %src to i32
|
||||
%res1 = fptosi float %src to i32
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @uitofp(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = uitofp i32 %src to float
|
||||
%res1 = uitofp i32 %src to float
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sitofp(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = sitofp i32 %src to float
|
||||
%res1 = sitofp i32 %src to float
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @ptrtoint(i32* %src){
|
||||
entry:
|
||||
; CHECK: %res1 = ptrtoint i32* %src to i8
|
||||
%res1 = ptrtoint i32* %src to i8
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @inttoptr(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = inttoptr i32 %src to i32*
|
||||
%res1 = inttoptr i32 %src to i32*
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @bitcast(i32 %src1, i32* %src2){
|
||||
entry:
|
||||
; CHECK: %res1 = bitcast i32 %src1 to i32
|
||||
%res1 = bitcast i32 %src1 to i32
|
||||
|
||||
; CHECK: %res2 = bitcast i32* %src2 to i64*
|
||||
%res2 = bitcast i32* %src2 to i64*
|
||||
|
||||
ret void
|
||||
}
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; conversionOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread conversion instructions from
|
||||
; older bitcode files.
|
||||
|
||||
define void @trunc(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = trunc i32 %src to i8
|
||||
%res1 = trunc i32 %src to i8
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @zext(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = zext i32 %src to i64
|
||||
%res1 = zext i32 %src to i64
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sext(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = sext i32 %src to i64
|
||||
%res1 = sext i32 %src to i64
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptrunc(double %src){
|
||||
entry:
|
||||
; CHECK: %res1 = fptrunc double %src to float
|
||||
%res1 = fptrunc double %src to float
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fpext(float %src){
|
||||
entry:
|
||||
; CHECK: %res1 = fpext float %src to double
|
||||
%res1 = fpext float %src to double
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptoui(float %src){
|
||||
entry:
|
||||
; CHECK: %res1 = fptoui float %src to i32
|
||||
%res1 = fptoui float %src to i32
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptosi(float %src){
|
||||
entry:
|
||||
; CHECK: %res1 = fptosi float %src to i32
|
||||
%res1 = fptosi float %src to i32
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @uitofp(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = uitofp i32 %src to float
|
||||
%res1 = uitofp i32 %src to float
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sitofp(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = sitofp i32 %src to float
|
||||
%res1 = sitofp i32 %src to float
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @ptrtoint(i32* %src){
|
||||
entry:
|
||||
; CHECK: %res1 = ptrtoint i32* %src to i8
|
||||
%res1 = ptrtoint i32* %src to i8
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @inttoptr(i32 %src){
|
||||
entry:
|
||||
; CHECK: %res1 = inttoptr i32 %src to i32*
|
||||
%res1 = inttoptr i32 %src to i32*
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @bitcast(i32 %src1, i32* %src2){
|
||||
entry:
|
||||
; CHECK: %res1 = bitcast i32 %src1 to i32
|
||||
%res1 = bitcast i32 %src1 to i32
|
||||
|
||||
; CHECK: %res2 = bitcast i32* %src2 to i64*
|
||||
%res2 = bitcast i32* %src2 to i64*
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,328 +1,328 @@
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; memOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread memory related instructions of
|
||||
; older bitcode files.
|
||||
|
||||
define void @alloca(){
|
||||
entry:
|
||||
; CHECK: %res1 = alloca i8
|
||||
%res1 = alloca i8
|
||||
|
||||
; CHECK-NEXT: %res2 = alloca i8, i32 2
|
||||
%res2 = alloca i8, i32 2
|
||||
|
||||
; CHECK-NEXT: %res3 = alloca i8, i32 2, align 4
|
||||
%res3 = alloca i8, i32 2, align 4
|
||||
|
||||
; CHECK-NEXT: %res4 = alloca i8, align 4
|
||||
%res4 = alloca i8, align 4
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load(){
|
||||
entry:
|
||||
%ptr1 = alloca i8
|
||||
store i8 2, i8* %ptr1
|
||||
|
||||
; CHECK: %res1 = load i8* %ptr1
|
||||
%res1 = load i8* %ptr1
|
||||
|
||||
; CHECK-NEXT: %res2 = load volatile i8* %ptr1
|
||||
%res2 = load volatile i8* %ptr1
|
||||
|
||||
; CHECK-NEXT: %res3 = load i8* %ptr1, align 1
|
||||
%res3 = load i8* %ptr1, align 1
|
||||
|
||||
; CHECK-NEXT: %res4 = load volatile i8* %ptr1, align 1
|
||||
%res4 = load volatile i8* %ptr1, align 1
|
||||
|
||||
; CHECK-NEXT: %res5 = load i8* %ptr1, !nontemporal !0
|
||||
%res5 = load i8* %ptr1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: %res6 = load volatile i8* %ptr1, !nontemporal !0
|
||||
%res6 = load volatile i8* %ptr1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: %res7 = load i8* %ptr1, align 1, !nontemporal !0
|
||||
%res7 = load i8* %ptr1, align 1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: %res8 = load volatile i8* %ptr1, align 1, !nontemporal !0
|
||||
%res8 = load volatile i8* %ptr1, align 1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: %res9 = load i8* %ptr1, !invariant.load !1
|
||||
%res9 = load i8* %ptr1, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res10 = load volatile i8* %ptr1, !invariant.load !1
|
||||
%res10 = load volatile i8* %ptr1, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res11 = load i8* %ptr1, align 1, !invariant.load !1
|
||||
%res11 = load i8* %ptr1, align 1, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res12 = load volatile i8* %ptr1, align 1, !invariant.load !1
|
||||
%res12 = load volatile i8* %ptr1, align 1, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res13 = load i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
|
||||
%res13 = load i8* %ptr1, !nontemporal !0, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res14 = load volatile i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
|
||||
%res14 = load volatile i8* %ptr1, !nontemporal !0, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res15 = load i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
|
||||
%res15 = load i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res16 = load volatile i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
|
||||
%res16 = load volatile i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @loadAtomic(){
|
||||
entry:
|
||||
%ptr1 = alloca i8
|
||||
store i8 2, i8* %ptr1
|
||||
|
||||
; CHECK: %res1 = load atomic i8* %ptr1 unordered, align 1
|
||||
%res1 = load atomic i8* %ptr1 unordered, align 1
|
||||
|
||||
; CHECK-NEXT: %res2 = load atomic i8* %ptr1 monotonic, align 1
|
||||
%res2 = load atomic i8* %ptr1 monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: %res3 = load atomic i8* %ptr1 acquire, align 1
|
||||
%res3 = load atomic i8* %ptr1 acquire, align 1
|
||||
|
||||
; CHECK-NEXT: %res4 = load atomic i8* %ptr1 seq_cst, align 1
|
||||
%res4 = load atomic i8* %ptr1 seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: %res5 = load atomic volatile i8* %ptr1 unordered, align 1
|
||||
%res5 = load atomic volatile i8* %ptr1 unordered, align 1
|
||||
|
||||
; CHECK-NEXT: %res6 = load atomic volatile i8* %ptr1 monotonic, align 1
|
||||
%res6 = load atomic volatile i8* %ptr1 monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: %res7 = load atomic volatile i8* %ptr1 acquire, align 1
|
||||
%res7 = load atomic volatile i8* %ptr1 acquire, align 1
|
||||
|
||||
; CHECK-NEXT: %res8 = load atomic volatile i8* %ptr1 seq_cst, align 1
|
||||
%res8 = load atomic volatile i8* %ptr1 seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: %res9 = load atomic i8* %ptr1 singlethread unordered, align 1
|
||||
%res9 = load atomic i8* %ptr1 singlethread unordered, align 1
|
||||
|
||||
; CHECK-NEXT: %res10 = load atomic i8* %ptr1 singlethread monotonic, align 1
|
||||
%res10 = load atomic i8* %ptr1 singlethread monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: %res11 = load atomic i8* %ptr1 singlethread acquire, align 1
|
||||
%res11 = load atomic i8* %ptr1 singlethread acquire, align 1
|
||||
|
||||
; CHECK-NEXT: %res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1
|
||||
%res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: %res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1
|
||||
%res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1
|
||||
|
||||
; CHECK-NEXT: %res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1
|
||||
%res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: %res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1
|
||||
%res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1
|
||||
|
||||
; CHECK-NEXT: %res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1
|
||||
%res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store(){
|
||||
entry:
|
||||
%ptr1 = alloca i8
|
||||
|
||||
; CHECK: store i8 2, i8* %ptr1
|
||||
store i8 2, i8* %ptr1
|
||||
|
||||
; CHECK-NEXT: store volatile i8 2, i8* %ptr1
|
||||
store volatile i8 2, i8* %ptr1
|
||||
|
||||
; CHECK-NEXT: store i8 2, i8* %ptr1, align 1
|
||||
store i8 2, i8* %ptr1, align 1
|
||||
|
||||
; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1
|
||||
store volatile i8 2, i8* %ptr1, align 1
|
||||
|
||||
; CHECK-NEXT: store i8 2, i8* %ptr1, !nontemporal !0
|
||||
store i8 2, i8* %ptr1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: store volatile i8 2, i8* %ptr1, !nontemporal !0
|
||||
store volatile i8 2, i8* %ptr1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: store i8 2, i8* %ptr1, align 1, !nontemporal !0
|
||||
store i8 2, i8* %ptr1, align 1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
|
||||
store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @storeAtomic(){
|
||||
entry:
|
||||
%ptr1 = alloca i8
|
||||
|
||||
; CHECK: store atomic i8 2, i8* %ptr1 unordered, align 1
|
||||
store atomic i8 2, i8* %ptr1 unordered, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 monotonic, align 1
|
||||
store atomic i8 2, i8* %ptr1 monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 release, align 1
|
||||
store atomic i8 2, i8* %ptr1 release, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 seq_cst, align 1
|
||||
store atomic i8 2, i8* %ptr1 seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 unordered, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 unordered, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 monotonic, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 release, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 release, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 seq_cst, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread unordered, align 1
|
||||
store atomic i8 2, i8* %ptr1 singlethread unordered, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread monotonic, align 1
|
||||
store atomic i8 2, i8* %ptr1 singlethread monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread release, align 1
|
||||
store atomic i8 2, i8* %ptr1 singlethread release, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread seq_cst, align 1
|
||||
store atomic i8 2, i8* %ptr1 singlethread seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread unordered, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 singlethread unordered, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread monotonic, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 singlethread monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread release, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 singlethread release, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread seq_cst, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 singlethread seq_cst, align 1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @cmpxchg(i32* %ptr,i32 %cmp,i32 %new){
|
||||
entry:
|
||||
;cmpxchg [volatile] <ty>* <pointer>, <ty> <cmp>, <ty> <new> [singlethread] <ordering>
|
||||
|
||||
; CHECK: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
|
||||
; CHECK-NEXT: %res1 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res1 = cmpxchg i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
|
||||
; CHECK-NEXT: %res2 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res2 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
|
||||
; CHECK-NEXT: %res3 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res3 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
|
||||
; CHECK-NEXT: %res4 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res4 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
|
||||
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire acquire
|
||||
; CHECK-NEXT: %res5 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res5 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acquire acquire
|
||||
; CHECK-NEXT: %res6 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res6 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acquire acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
|
||||
; CHECK-NEXT: %res7 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res7 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
|
||||
; CHECK-NEXT: %res8 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res8 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
|
||||
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new release monotonic
|
||||
; CHECK-NEXT: %res9 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res9 = cmpxchg i32* %ptr, i32 %cmp, i32 %new release monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release monotonic
|
||||
; CHECK-NEXT: %res10 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res10 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
|
||||
; CHECK-NEXT: %res11 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res11 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
|
||||
; CHECK-NEXT: %res12 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res12 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
|
||||
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
|
||||
; CHECK-NEXT: %res13 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res13 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
|
||||
; CHECK-NEXT: %res14 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res14 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
|
||||
; CHECK-NEXT: %res15 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
|
||||
; CHECK-NEXT: %res16 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res16 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
|
||||
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
|
||||
; CHECK-NEXT: %res17 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res17 = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
|
||||
; CHECK-NEXT: %res18 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res18 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
|
||||
; CHECK-NEXT: %res19 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res19 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
|
||||
; CHECK-NEXT: %res20 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res20 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @getelementptr({i8, i8}* %s, <4 x i8*> %ptrs, <4 x i64> %offsets ){
|
||||
entry:
|
||||
; CHECK: %res1 = getelementptr { i8, i8 }* %s, i32 1, i32 1
|
||||
%res1 = getelementptr {i8, i8}* %s, i32 1, i32 1
|
||||
|
||||
; CHECK-NEXT: %res2 = getelementptr inbounds { i8, i8 }* %s, i32 1, i32 1
|
||||
%res2 = getelementptr inbounds {i8, i8}* %s, i32 1, i32 1
|
||||
|
||||
; CHECK-NEXT: %res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets
|
||||
%res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
!0 = metadata !{ i32 1 }
|
||||
!1 = metadata !{}
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; memOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread memory related instructions of
|
||||
; older bitcode files.
|
||||
|
||||
define void @alloca(){
|
||||
entry:
|
||||
; CHECK: %res1 = alloca i8
|
||||
%res1 = alloca i8
|
||||
|
||||
; CHECK-NEXT: %res2 = alloca i8, i32 2
|
||||
%res2 = alloca i8, i32 2
|
||||
|
||||
; CHECK-NEXT: %res3 = alloca i8, i32 2, align 4
|
||||
%res3 = alloca i8, i32 2, align 4
|
||||
|
||||
; CHECK-NEXT: %res4 = alloca i8, align 4
|
||||
%res4 = alloca i8, align 4
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @load(){
|
||||
entry:
|
||||
%ptr1 = alloca i8
|
||||
store i8 2, i8* %ptr1
|
||||
|
||||
; CHECK: %res1 = load i8* %ptr1
|
||||
%res1 = load i8* %ptr1
|
||||
|
||||
; CHECK-NEXT: %res2 = load volatile i8* %ptr1
|
||||
%res2 = load volatile i8* %ptr1
|
||||
|
||||
; CHECK-NEXT: %res3 = load i8* %ptr1, align 1
|
||||
%res3 = load i8* %ptr1, align 1
|
||||
|
||||
; CHECK-NEXT: %res4 = load volatile i8* %ptr1, align 1
|
||||
%res4 = load volatile i8* %ptr1, align 1
|
||||
|
||||
; CHECK-NEXT: %res5 = load i8* %ptr1, !nontemporal !0
|
||||
%res5 = load i8* %ptr1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: %res6 = load volatile i8* %ptr1, !nontemporal !0
|
||||
%res6 = load volatile i8* %ptr1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: %res7 = load i8* %ptr1, align 1, !nontemporal !0
|
||||
%res7 = load i8* %ptr1, align 1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: %res8 = load volatile i8* %ptr1, align 1, !nontemporal !0
|
||||
%res8 = load volatile i8* %ptr1, align 1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: %res9 = load i8* %ptr1, !invariant.load !1
|
||||
%res9 = load i8* %ptr1, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res10 = load volatile i8* %ptr1, !invariant.load !1
|
||||
%res10 = load volatile i8* %ptr1, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res11 = load i8* %ptr1, align 1, !invariant.load !1
|
||||
%res11 = load i8* %ptr1, align 1, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res12 = load volatile i8* %ptr1, align 1, !invariant.load !1
|
||||
%res12 = load volatile i8* %ptr1, align 1, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res13 = load i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
|
||||
%res13 = load i8* %ptr1, !nontemporal !0, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res14 = load volatile i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
|
||||
%res14 = load volatile i8* %ptr1, !nontemporal !0, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res15 = load i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
|
||||
%res15 = load i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
|
||||
|
||||
; CHECK-NEXT: %res16 = load volatile i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
|
||||
%res16 = load volatile i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @loadAtomic(){
|
||||
entry:
|
||||
%ptr1 = alloca i8
|
||||
store i8 2, i8* %ptr1
|
||||
|
||||
; CHECK: %res1 = load atomic i8* %ptr1 unordered, align 1
|
||||
%res1 = load atomic i8* %ptr1 unordered, align 1
|
||||
|
||||
; CHECK-NEXT: %res2 = load atomic i8* %ptr1 monotonic, align 1
|
||||
%res2 = load atomic i8* %ptr1 monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: %res3 = load atomic i8* %ptr1 acquire, align 1
|
||||
%res3 = load atomic i8* %ptr1 acquire, align 1
|
||||
|
||||
; CHECK-NEXT: %res4 = load atomic i8* %ptr1 seq_cst, align 1
|
||||
%res4 = load atomic i8* %ptr1 seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: %res5 = load atomic volatile i8* %ptr1 unordered, align 1
|
||||
%res5 = load atomic volatile i8* %ptr1 unordered, align 1
|
||||
|
||||
; CHECK-NEXT: %res6 = load atomic volatile i8* %ptr1 monotonic, align 1
|
||||
%res6 = load atomic volatile i8* %ptr1 monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: %res7 = load atomic volatile i8* %ptr1 acquire, align 1
|
||||
%res7 = load atomic volatile i8* %ptr1 acquire, align 1
|
||||
|
||||
; CHECK-NEXT: %res8 = load atomic volatile i8* %ptr1 seq_cst, align 1
|
||||
%res8 = load atomic volatile i8* %ptr1 seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: %res9 = load atomic i8* %ptr1 singlethread unordered, align 1
|
||||
%res9 = load atomic i8* %ptr1 singlethread unordered, align 1
|
||||
|
||||
; CHECK-NEXT: %res10 = load atomic i8* %ptr1 singlethread monotonic, align 1
|
||||
%res10 = load atomic i8* %ptr1 singlethread monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: %res11 = load atomic i8* %ptr1 singlethread acquire, align 1
|
||||
%res11 = load atomic i8* %ptr1 singlethread acquire, align 1
|
||||
|
||||
; CHECK-NEXT: %res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1
|
||||
%res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: %res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1
|
||||
%res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1
|
||||
|
||||
; CHECK-NEXT: %res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1
|
||||
%res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: %res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1
|
||||
%res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1
|
||||
|
||||
; CHECK-NEXT: %res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1
|
||||
%res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store(){
|
||||
entry:
|
||||
%ptr1 = alloca i8
|
||||
|
||||
; CHECK: store i8 2, i8* %ptr1
|
||||
store i8 2, i8* %ptr1
|
||||
|
||||
; CHECK-NEXT: store volatile i8 2, i8* %ptr1
|
||||
store volatile i8 2, i8* %ptr1
|
||||
|
||||
; CHECK-NEXT: store i8 2, i8* %ptr1, align 1
|
||||
store i8 2, i8* %ptr1, align 1
|
||||
|
||||
; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1
|
||||
store volatile i8 2, i8* %ptr1, align 1
|
||||
|
||||
; CHECK-NEXT: store i8 2, i8* %ptr1, !nontemporal !0
|
||||
store i8 2, i8* %ptr1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: store volatile i8 2, i8* %ptr1, !nontemporal !0
|
||||
store volatile i8 2, i8* %ptr1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: store i8 2, i8* %ptr1, align 1, !nontemporal !0
|
||||
store i8 2, i8* %ptr1, align 1, !nontemporal !0
|
||||
|
||||
; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
|
||||
store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @storeAtomic(){
|
||||
entry:
|
||||
%ptr1 = alloca i8
|
||||
|
||||
; CHECK: store atomic i8 2, i8* %ptr1 unordered, align 1
|
||||
store atomic i8 2, i8* %ptr1 unordered, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 monotonic, align 1
|
||||
store atomic i8 2, i8* %ptr1 monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 release, align 1
|
||||
store atomic i8 2, i8* %ptr1 release, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 seq_cst, align 1
|
||||
store atomic i8 2, i8* %ptr1 seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 unordered, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 unordered, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 monotonic, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 release, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 release, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 seq_cst, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread unordered, align 1
|
||||
store atomic i8 2, i8* %ptr1 singlethread unordered, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread monotonic, align 1
|
||||
store atomic i8 2, i8* %ptr1 singlethread monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread release, align 1
|
||||
store atomic i8 2, i8* %ptr1 singlethread release, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread seq_cst, align 1
|
||||
store atomic i8 2, i8* %ptr1 singlethread seq_cst, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread unordered, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 singlethread unordered, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread monotonic, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 singlethread monotonic, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread release, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 singlethread release, align 1
|
||||
|
||||
; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread seq_cst, align 1
|
||||
store atomic volatile i8 2, i8* %ptr1 singlethread seq_cst, align 1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @cmpxchg(i32* %ptr,i32 %cmp,i32 %new){
|
||||
entry:
|
||||
;cmpxchg [volatile] <ty>* <pointer>, <ty> <cmp>, <ty> <new> [singlethread] <ordering>
|
||||
|
||||
; CHECK: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
|
||||
; CHECK-NEXT: %res1 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res1 = cmpxchg i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
|
||||
; CHECK-NEXT: %res2 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res2 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
|
||||
; CHECK-NEXT: %res3 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res3 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
|
||||
; CHECK-NEXT: %res4 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res4 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
|
||||
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire acquire
|
||||
; CHECK-NEXT: %res5 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res5 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acquire acquire
|
||||
; CHECK-NEXT: %res6 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res6 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acquire acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
|
||||
; CHECK-NEXT: %res7 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res7 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
|
||||
; CHECK-NEXT: %res8 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res8 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
|
||||
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new release monotonic
|
||||
; CHECK-NEXT: %res9 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res9 = cmpxchg i32* %ptr, i32 %cmp, i32 %new release monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release monotonic
|
||||
; CHECK-NEXT: %res10 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res10 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
|
||||
; CHECK-NEXT: %res11 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res11 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
|
||||
; CHECK-NEXT: %res12 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res12 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
|
||||
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
|
||||
; CHECK-NEXT: %res13 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res13 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
|
||||
; CHECK-NEXT: %res14 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res14 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
|
||||
; CHECK-NEXT: %res15 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
|
||||
; CHECK-NEXT: %res16 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res16 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
|
||||
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
|
||||
; CHECK-NEXT: %res17 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res17 = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
|
||||
; CHECK-NEXT: %res18 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res18 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
|
||||
; CHECK-NEXT: %res19 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res19 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
|
||||
|
||||
; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
|
||||
; CHECK-NEXT: %res20 = extractvalue { i32, i1 } [[TMP]], 0
|
||||
%res20 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @getelementptr({i8, i8}* %s, <4 x i8*> %ptrs, <4 x i64> %offsets ){
|
||||
entry:
|
||||
; CHECK: %res1 = getelementptr { i8, i8 }* %s, i32 1, i32 1
|
||||
%res1 = getelementptr {i8, i8}* %s, i32 1, i32 1
|
||||
|
||||
; CHECK-NEXT: %res2 = getelementptr inbounds { i8, i8 }* %s, i32 1, i32 1
|
||||
%res2 = getelementptr inbounds {i8, i8}* %s, i32 1, i32 1
|
||||
|
||||
; CHECK-NEXT: %res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets
|
||||
%res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
!0 = metadata !{ i32 1 }
|
||||
!1 = metadata !{}
|
||||
|
||||
@ -1,47 +1,47 @@
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread terminator instructions from
|
||||
; older bitcode files.
|
||||
|
||||
define i32 @condbr(i1 %cond){
|
||||
entry:
|
||||
; CHECK: br i1 %cond, label %TrueLabel, label %FalseLabel
|
||||
br i1 %cond, label %TrueLabel, label %FalseLabel
|
||||
|
||||
TrueLabel:
|
||||
ret i32 1
|
||||
|
||||
FalseLabel:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define i32 @uncondbr(){
|
||||
entry:
|
||||
; CHECK: br label %uncondLabel
|
||||
br label %uncondLabel
|
||||
|
||||
uncondLabel:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
define i32 @indirectbr(i8* %Addr){
|
||||
entry:
|
||||
; CHECK: indirectbr i8* %Addr, [label %bb1, label %bb2]
|
||||
indirectbr i8* %Addr, [ label %bb1, label %bb2 ]
|
||||
|
||||
bb1:
|
||||
ret i32 1
|
||||
|
||||
bb2:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define void @unreachable(){
|
||||
entry:
|
||||
; CHECK: unreachable
|
||||
unreachable
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread terminator instructions from
|
||||
; older bitcode files.
|
||||
|
||||
define i32 @condbr(i1 %cond){
|
||||
entry:
|
||||
; CHECK: br i1 %cond, label %TrueLabel, label %FalseLabel
|
||||
br i1 %cond, label %TrueLabel, label %FalseLabel
|
||||
|
||||
TrueLabel:
|
||||
ret i32 1
|
||||
|
||||
FalseLabel:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define i32 @uncondbr(){
|
||||
entry:
|
||||
; CHECK: br label %uncondLabel
|
||||
br label %uncondLabel
|
||||
|
||||
uncondLabel:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
define i32 @indirectbr(i8* %Addr){
|
||||
entry:
|
||||
; CHECK: indirectbr i8* %Addr, [label %bb1, label %bb2]
|
||||
indirectbr i8* %Addr, [ label %bb1, label %bb2 ]
|
||||
|
||||
bb1:
|
||||
ret i32 1
|
||||
|
||||
bb2:
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define void @unreachable(){
|
||||
entry:
|
||||
; CHECK: unreachable
|
||||
unreachable
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
@ -1,34 +1,32 @@
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread vector operations of
|
||||
; older bitcode files.
|
||||
|
||||
define void @extractelement(<2 x i8> %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0
|
||||
%res1 = extractelement <2 x i8> %x1, i32 0
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @insertelement(<2 x i8> %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0
|
||||
%res1 = insertelement <2 x i8> %x1, i8 0, i32 0
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @shufflevector(<2 x i8> %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
|
||||
%res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
|
||||
|
||||
; CHECK-NEXT: %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>
|
||||
%res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; RUN: llvm-dis < %s.bc| FileCheck %s
|
||||
|
||||
; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
||||
; The test checks that LLVM does not misread vector operations of
|
||||
; older bitcode files.
|
||||
|
||||
define void @extractelement(<2 x i8> %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0
|
||||
%res1 = extractelement <2 x i8> %x1, i32 0
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @insertelement(<2 x i8> %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0
|
||||
%res1 = insertelement <2 x i8> %x1, i8 0, i32 0
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @shufflevector(<2 x i8> %x1){
|
||||
entry:
|
||||
; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
|
||||
%res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
|
||||
|
||||
; CHECK-NEXT: %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>
|
||||
%res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user