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[AArch64] Add v8.1a "Virtualization Host Extensions"
Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8500 Patch by: Tom Coxon llvm-svn: 235107
This commit is contained in:
Vladimir Sukharev
parent
88f8dd76ed
commit
252dc858c6
@ -771,7 +771,36 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings
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{"lorea_el1", LOREA_EL1, AArch64::HasV8_1aOps},
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{"lorn_el1", LORN_EL1, AArch64::HasV8_1aOps},
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{"lorc_el1", LORC_EL1, AArch64::HasV8_1aOps},
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{"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
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{"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
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// v8.1a "Virtualization host extensions" system registers
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{"ttbr1_el2", TTBR1_EL2, AArch64::HasV8_1aOps},
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{"contextidr_el2", CONTEXTIDR_EL2, AArch64::HasV8_1aOps},
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{"cnthv_tval_el2", CNTHV_TVAL_EL2, AArch64::HasV8_1aOps},
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{"cnthv_cval_el2", CNTHV_CVAL_EL2, AArch64::HasV8_1aOps},
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{"cnthv_ctl_el2", CNTHV_CTL_EL2, AArch64::HasV8_1aOps},
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{"sctlr_el12", SCTLR_EL12, AArch64::HasV8_1aOps},
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{"cpacr_el12", CPACR_EL12, AArch64::HasV8_1aOps},
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{"ttbr0_el12", TTBR0_EL12, AArch64::HasV8_1aOps},
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{"ttbr1_el12", TTBR1_EL12, AArch64::HasV8_1aOps},
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{"tcr_el12", TCR_EL12, AArch64::HasV8_1aOps},
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{"afsr0_el12", AFSR0_EL12, AArch64::HasV8_1aOps},
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{"afsr1_el12", AFSR1_EL12, AArch64::HasV8_1aOps},
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{"esr_el12", ESR_EL12, AArch64::HasV8_1aOps},
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{"far_el12", FAR_EL12, AArch64::HasV8_1aOps},
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{"mair_el12", MAIR_EL12, AArch64::HasV8_1aOps},
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{"amair_el12", AMAIR_EL12, AArch64::HasV8_1aOps},
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{"vbar_el12", VBAR_EL12, AArch64::HasV8_1aOps},
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{"contextidr_el12", CONTEXTIDR_EL12, AArch64::HasV8_1aOps},
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{"cntkctl_el12", CNTKCTL_EL12, AArch64::HasV8_1aOps},
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{"cntp_tval_el02", CNTP_TVAL_EL02, AArch64::HasV8_1aOps},
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{"cntp_ctl_el02", CNTP_CTL_EL02, AArch64::HasV8_1aOps},
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{"cntp_cval_el02", CNTP_CVAL_EL02, AArch64::HasV8_1aOps},
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{"cntv_tval_el02", CNTV_TVAL_EL02, AArch64::HasV8_1aOps},
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{"cntv_ctl_el02", CNTV_CTL_EL02, AArch64::HasV8_1aOps},
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{"cntv_cval_el02", CNTV_CVAL_EL02, AArch64::HasV8_1aOps},
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{"spsr_el12", SPSR_EL12, AArch64::HasV8_1aOps},
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{"elr_el12", ELR_EL12, AArch64::HasV8_1aOps},
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};
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uint32_t
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@ -1148,6 +1148,35 @@ namespace AArch64SysReg {
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LORC_EL1 = 0xc523, // 11 000 1010 0100 011
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LORID_EL1 = 0xc527, // 11 000 1010 0100 111
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// v8.1a "Virtualization host extensions" system registers
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TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001
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CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001
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CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000
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CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010
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CNTHV_CTL_EL2 = 0xe719, // 11 100 1110 0011 001
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SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000
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CPACR_EL12 = 0xe882, // 11 101 0001 0000 010
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TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000
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TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001
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TCR_EL12 = 0xe902, // 11 101 0010 0000 010
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AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000
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AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001
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ESR_EL12 = 0xea90, // 11 101 0101 0010 000
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FAR_EL12 = 0xeb00, // 11 101 0110 0000 000
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MAIR_EL12 = 0xed10, // 11 101 1010 0010 000
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AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000
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VBAR_EL12 = 0xee00, // 11 101 1100 0000 000
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CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001
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CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000
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CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000
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CNTP_CTL_EL02 = 0xef11, // 11 101 1110 0010 001
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CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010
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CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000
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CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001
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CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010
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SPSR_EL12 = 0xea00, // 11 101 0100 0000 000
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ELR_EL12 = 0xea01, // 11 101 0100 0000 001
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// Cyclone specific system registers
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CPM_IOACC_CTL_EL3 = 0xff90,
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};
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61
test/MC/AArch64/armv8.1a-vhe.s
Normal file
61
test/MC/AArch64/armv8.1a-vhe.s
Normal file
@ -0,0 +1,61 @@
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s
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//------------------------------------------------------------------------------
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// Virtualization Host Extensions
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//------------------------------------------------------------------------------
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msr TTBR1_EL2, x0
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msr CONTEXTIDR_EL2, x0
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msr CNTHV_TVAL_EL2, x0
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msr CNTHV_CVAL_EL2, x0
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msr CNTHV_CTL_EL2, x0
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msr SCTLR_EL12, x0
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msr CPACR_EL12, x0
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msr TTBR0_EL12, x0
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msr TTBR1_EL12, x0
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msr TCR_EL12, x0
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msr AFSR0_EL12, x0
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msr AFSR1_EL12, x0
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msr ESR_EL12, x0
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msr FAR_EL12, x0
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msr MAIR_EL12, x0
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msr AMAIR_EL12, x0
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msr VBAR_EL12, x0
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msr CONTEXTIDR_EL12, x0
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msr CNTKCTL_EL12, x0
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msr CNTP_TVAL_EL02, x0
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msr CNTP_CTL_EL02, x0
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msr CNTP_CVAL_EL02, x0
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msr CNTV_TVAL_EL02, x0
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msr CNTV_CTL_EL02, x0
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msr CNTV_CVAL_EL02, x0
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msr SPSR_EL12, x0
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msr ELR_EL12, x0
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// CHECK: msr TTBR1_EL2, x0 // encoding: [0x20,0x20,0x1c,0xd5]
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// CHECK: msr CONTEXTIDR_EL2, x0 // encoding: [0x20,0xd0,0x1c,0xd5]
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// CHECK: msr CNTHV_TVAL_EL2, x0 // encoding: [0x00,0xe3,0x1c,0xd5]
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// CHECK: msr CNTHV_CVAL_EL2, x0 // encoding: [0x40,0xe3,0x1c,0xd5]
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// CHECK: msr CNTHV_CTL_EL2, x0 // encoding: [0x20,0xe3,0x1c,0xd5]
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// CHECK: msr SCTLR_EL12, x0 // encoding: [0x00,0x10,0x1d,0xd5]
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// CHECK: msr CPACR_EL12, x0 // encoding: [0x40,0x10,0x1d,0xd5]
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// CHECK: msr TTBR0_EL12, x0 // encoding: [0x00,0x20,0x1d,0xd5]
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// CHECK: msr TTBR1_EL12, x0 // encoding: [0x20,0x20,0x1d,0xd5]
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// CHECK: msr TCR_EL12, x0 // encoding: [0x40,0x20,0x1d,0xd5]
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// CHECK: msr AFSR0_EL12, x0 // encoding: [0x00,0x51,0x1d,0xd5]
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// CHECK: msr AFSR1_EL12, x0 // encoding: [0x20,0x51,0x1d,0xd5]
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// CHECK: msr ESR_EL12, x0 // encoding: [0x00,0x52,0x1d,0xd5]
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// CHECK: msr FAR_EL12, x0 // encoding: [0x00,0x60,0x1d,0xd5]
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// CHECK: msr MAIR_EL12, x0 // encoding: [0x00,0xa2,0x1d,0xd5]
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// CHECK: msr AMAIR_EL12, x0 // encoding: [0x00,0xa3,0x1d,0xd5]
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// CHECK: msr VBAR_EL12, x0 // encoding: [0x00,0xc0,0x1d,0xd5]
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// CHECK: msr CONTEXTIDR_EL12, x0 // encoding: [0x20,0xd0,0x1d,0xd5]
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// CHECK: msr CNTKCTL_EL12, x0 // encoding: [0x00,0xe1,0x1d,0xd5]
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// CHECK: msr CNTP_TVAL_EL02, x0 // encoding: [0x00,0xe2,0x1d,0xd5]
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// CHECK: msr CNTP_CTL_EL02, x0 // encoding: [0x20,0xe2,0x1d,0xd5]
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// CHECK: msr CNTP_CVAL_EL02, x0 // encoding: [0x40,0xe2,0x1d,0xd5]
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// CHECK: msr CNTV_TVAL_EL02, x0 // encoding: [0x00,0xe3,0x1d,0xd5]
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// CHECK: msr CNTV_CTL_EL02, x0 // encoding: [0x20,0xe3,0x1d,0xd5]
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// CHECK: msr CNTV_CVAL_EL02, x0 // encoding: [0x40,0xe3,0x1d,0xd5]
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// CHECK: msr SPSR_EL12, x0 // encoding: [0x00,0x40,0x1d,0xd5]
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// CHECK: msr ELR_EL12, x0 // encoding: [0x20,0x40,0x1d,0xd5]
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56
test/MC/Disassembler/AArch64/armv8.1a-vhe.txt
Normal file
56
test/MC/Disassembler/AArch64/armv8.1a-vhe.txt
Normal file
@ -0,0 +1,56 @@
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# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
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0x20,0x20,0x1c,0xd5
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0x20,0xd0,0x1c,0xd5
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0x00,0xe3,0x1c,0xd5
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0x40,0xe3,0x1c,0xd5
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0x20,0xe3,0x1c,0xd5
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0x00,0x10,0x1d,0xd5
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0x40,0x10,0x1d,0xd5
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0x00,0x20,0x1d,0xd5
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0x20,0x20,0x1d,0xd5
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0x40,0x20,0x1d,0xd5
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0x00,0x51,0x1d,0xd5
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0x20,0x51,0x1d,0xd5
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0x00,0x52,0x1d,0xd5
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0x00,0x60,0x1d,0xd5
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0x00,0xa2,0x1d,0xd5
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0x00,0xa3,0x1d,0xd5
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0x00,0xc0,0x1d,0xd5
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0x20,0xd0,0x1d,0xd5
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0x00,0xe1,0x1d,0xd5
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0x00,0xe2,0x1d,0xd5
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0x20,0xe2,0x1d,0xd5
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0x40,0xe2,0x1d,0xd5
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0x00,0xe3,0x1d,0xd5
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0x20,0xe3,0x1d,0xd5
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0x40,0xe3,0x1d,0xd5
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0x00,0x40,0x1d,0xd5
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0x20,0x40,0x1d,0xd5
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# CHECK: msr TTBR1_EL2, x0
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# CHECK: msr CONTEXTIDR_EL2, x0
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# CHECK: msr CNTHV_TVAL_EL2, x0
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# CHECK: msr CNTHV_CVAL_EL2, x0
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# CHECK: msr CNTHV_CTL_EL2, x0
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# CHECK: msr SCTLR_EL12, x0
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# CHECK: msr CPACR_EL12, x0
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# CHECK: msr TTBR0_EL12, x0
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# CHECK: msr TTBR1_EL12, x0
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# CHECK: msr TCR_EL12, x0
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# CHECK: msr AFSR0_EL12, x0
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# CHECK: msr AFSR1_EL12, x0
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# CHECK: msr ESR_EL12, x0
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# CHECK: msr FAR_EL12, x0
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# CHECK: msr MAIR_EL12, x0
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# CHECK: msr AMAIR_EL12, x0
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# CHECK: msr VBAR_EL12, x0
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# CHECK: msr CONTEXTIDR_EL12, x0
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# CHECK: msr CNTKCTL_EL12, x0
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# CHECK: msr CNTP_TVAL_EL02, x0
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# CHECK: msr CNTP_CTL_EL02, x0
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# CHECK: msr CNTP_CVAL_EL02, x0
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# CHECK: msr CNTV_TVAL_EL02, x0
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# CHECK: msr CNTV_CTL_EL02, x0
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# CHECK: msr CNTV_CVAL_EL02, x0
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# CHECK: msr SPSR_EL12, x0
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# CHECK: msr ELR_EL12, x0
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