mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 11:42:57 +01:00
AArch64: implement ETMv4 trace system registers.
llvm-svn: 178637
This commit is contained in:
Tim Northover
parent
379439a23a
commit
2550df2b22
@ -196,6 +196,44 @@ const NamedImmMapper::Mapping A64SysReg::MRSMapper::MRSPairs[] = {
|
|||||||
{"cntpct_el0", CNTPCT_EL0},
|
{"cntpct_el0", CNTPCT_EL0},
|
||||||
{"cntvct_el0", CNTVCT_EL0},
|
{"cntvct_el0", CNTVCT_EL0},
|
||||||
|
|
||||||
|
// Trace registers
|
||||||
|
{"trcstatr", TRCSTATR},
|
||||||
|
{"trcidr8", TRCIDR8},
|
||||||
|
{"trcidr9", TRCIDR9},
|
||||||
|
{"trcidr10", TRCIDR10},
|
||||||
|
{"trcidr11", TRCIDR11},
|
||||||
|
{"trcidr12", TRCIDR12},
|
||||||
|
{"trcidr13", TRCIDR13},
|
||||||
|
{"trcidr0", TRCIDR0},
|
||||||
|
{"trcidr1", TRCIDR1},
|
||||||
|
{"trcidr2", TRCIDR2},
|
||||||
|
{"trcidr3", TRCIDR3},
|
||||||
|
{"trcidr4", TRCIDR4},
|
||||||
|
{"trcidr5", TRCIDR5},
|
||||||
|
{"trcidr6", TRCIDR6},
|
||||||
|
{"trcidr7", TRCIDR7},
|
||||||
|
{"trcoslsr", TRCOSLSR},
|
||||||
|
{"trcpdsr", TRCPDSR},
|
||||||
|
{"trcdevaff0", TRCDEVAFF0},
|
||||||
|
{"trcdevaff1", TRCDEVAFF1},
|
||||||
|
{"trclsr", TRCLSR},
|
||||||
|
{"trcauthstatus", TRCAUTHSTATUS},
|
||||||
|
{"trcdevarch", TRCDEVARCH},
|
||||||
|
{"trcdevid", TRCDEVID},
|
||||||
|
{"trcdevtype", TRCDEVTYPE},
|
||||||
|
{"trcpidr4", TRCPIDR4},
|
||||||
|
{"trcpidr5", TRCPIDR5},
|
||||||
|
{"trcpidr6", TRCPIDR6},
|
||||||
|
{"trcpidr7", TRCPIDR7},
|
||||||
|
{"trcpidr0", TRCPIDR0},
|
||||||
|
{"trcpidr1", TRCPIDR1},
|
||||||
|
{"trcpidr2", TRCPIDR2},
|
||||||
|
{"trcpidr3", TRCPIDR3},
|
||||||
|
{"trccidr0", TRCCIDR0},
|
||||||
|
{"trccidr1", TRCCIDR1},
|
||||||
|
{"trccidr2", TRCCIDR2},
|
||||||
|
{"trccidr3", TRCCIDR3},
|
||||||
|
|
||||||
// GICv3 registers
|
// GICv3 registers
|
||||||
{"icc_iar1_el1", ICC_IAR1_EL1},
|
{"icc_iar1_el1", ICC_IAR1_EL1},
|
||||||
{"icc_iar0_el1", ICC_IAR0_EL1},
|
{"icc_iar0_el1", ICC_IAR0_EL1},
|
||||||
@ -217,6 +255,10 @@ const NamedImmMapper::Mapping A64SysReg::MSRMapper::MSRPairs[] = {
|
|||||||
{"oslar_el1", OSLAR_EL1},
|
{"oslar_el1", OSLAR_EL1},
|
||||||
{"pmswinc_el0", PMSWINC_EL0},
|
{"pmswinc_el0", PMSWINC_EL0},
|
||||||
|
|
||||||
|
// Trace registers
|
||||||
|
{"trcoslar", TRCOSLAR},
|
||||||
|
{"trclar", TRCLAR},
|
||||||
|
|
||||||
// GICv3 registers
|
// GICv3 registers
|
||||||
{"icc_eoir1_el1", ICC_EOIR1_EL1},
|
{"icc_eoir1_el1", ICC_EOIR1_EL1},
|
||||||
{"icc_eoir0_el1", ICC_EOIR0_EL1},
|
{"icc_eoir0_el1", ICC_EOIR0_EL1},
|
||||||
@ -486,6 +528,180 @@ const NamedImmMapper::Mapping A64SysReg::SysRegMapper::SysRegPairs[] = {
|
|||||||
{"pmevtyper29_el0", PMEVTYPER29_EL0},
|
{"pmevtyper29_el0", PMEVTYPER29_EL0},
|
||||||
{"pmevtyper30_el0", PMEVTYPER30_EL0},
|
{"pmevtyper30_el0", PMEVTYPER30_EL0},
|
||||||
|
|
||||||
|
// Trace registers
|
||||||
|
{"trcprgctlr", TRCPRGCTLR},
|
||||||
|
{"trcprocselr", TRCPROCSELR},
|
||||||
|
{"trcconfigr", TRCCONFIGR},
|
||||||
|
{"trcauxctlr", TRCAUXCTLR},
|
||||||
|
{"trceventctl0r", TRCEVENTCTL0R},
|
||||||
|
{"trceventctl1r", TRCEVENTCTL1R},
|
||||||
|
{"trcstallctlr", TRCSTALLCTLR},
|
||||||
|
{"trctsctlr", TRCTSCTLR},
|
||||||
|
{"trcsyncpr", TRCSYNCPR},
|
||||||
|
{"trcccctlr", TRCCCCTLR},
|
||||||
|
{"trcbbctlr", TRCBBCTLR},
|
||||||
|
{"trctraceidr", TRCTRACEIDR},
|
||||||
|
{"trcqctlr", TRCQCTLR},
|
||||||
|
{"trcvictlr", TRCVICTLR},
|
||||||
|
{"trcviiectlr", TRCVIIECTLR},
|
||||||
|
{"trcvissctlr", TRCVISSCTLR},
|
||||||
|
{"trcvipcssctlr", TRCVIPCSSCTLR},
|
||||||
|
{"trcvdctlr", TRCVDCTLR},
|
||||||
|
{"trcvdsacctlr", TRCVDSACCTLR},
|
||||||
|
{"trcvdarcctlr", TRCVDARCCTLR},
|
||||||
|
{"trcseqevr0", TRCSEQEVR0},
|
||||||
|
{"trcseqevr1", TRCSEQEVR1},
|
||||||
|
{"trcseqevr2", TRCSEQEVR2},
|
||||||
|
{"trcseqrstevr", TRCSEQRSTEVR},
|
||||||
|
{"trcseqstr", TRCSEQSTR},
|
||||||
|
{"trcextinselr", TRCEXTINSELR},
|
||||||
|
{"trccntrldvr0", TRCCNTRLDVR0},
|
||||||
|
{"trccntrldvr1", TRCCNTRLDVR1},
|
||||||
|
{"trccntrldvr2", TRCCNTRLDVR2},
|
||||||
|
{"trccntrldvr3", TRCCNTRLDVR3},
|
||||||
|
{"trccntctlr0", TRCCNTCTLR0},
|
||||||
|
{"trccntctlr1", TRCCNTCTLR1},
|
||||||
|
{"trccntctlr2", TRCCNTCTLR2},
|
||||||
|
{"trccntctlr3", TRCCNTCTLR3},
|
||||||
|
{"trccntvr0", TRCCNTVR0},
|
||||||
|
{"trccntvr1", TRCCNTVR1},
|
||||||
|
{"trccntvr2", TRCCNTVR2},
|
||||||
|
{"trccntvr3", TRCCNTVR3},
|
||||||
|
{"trcimspec0", TRCIMSPEC0},
|
||||||
|
{"trcimspec1", TRCIMSPEC1},
|
||||||
|
{"trcimspec2", TRCIMSPEC2},
|
||||||
|
{"trcimspec3", TRCIMSPEC3},
|
||||||
|
{"trcimspec4", TRCIMSPEC4},
|
||||||
|
{"trcimspec5", TRCIMSPEC5},
|
||||||
|
{"trcimspec6", TRCIMSPEC6},
|
||||||
|
{"trcimspec7", TRCIMSPEC7},
|
||||||
|
{"trcrsctlr2", TRCRSCTLR2},
|
||||||
|
{"trcrsctlr3", TRCRSCTLR3},
|
||||||
|
{"trcrsctlr4", TRCRSCTLR4},
|
||||||
|
{"trcrsctlr5", TRCRSCTLR5},
|
||||||
|
{"trcrsctlr6", TRCRSCTLR6},
|
||||||
|
{"trcrsctlr7", TRCRSCTLR7},
|
||||||
|
{"trcrsctlr8", TRCRSCTLR8},
|
||||||
|
{"trcrsctlr9", TRCRSCTLR9},
|
||||||
|
{"trcrsctlr10", TRCRSCTLR10},
|
||||||
|
{"trcrsctlr11", TRCRSCTLR11},
|
||||||
|
{"trcrsctlr12", TRCRSCTLR12},
|
||||||
|
{"trcrsctlr13", TRCRSCTLR13},
|
||||||
|
{"trcrsctlr14", TRCRSCTLR14},
|
||||||
|
{"trcrsctlr15", TRCRSCTLR15},
|
||||||
|
{"trcrsctlr16", TRCRSCTLR16},
|
||||||
|
{"trcrsctlr17", TRCRSCTLR17},
|
||||||
|
{"trcrsctlr18", TRCRSCTLR18},
|
||||||
|
{"trcrsctlr19", TRCRSCTLR19},
|
||||||
|
{"trcrsctlr20", TRCRSCTLR20},
|
||||||
|
{"trcrsctlr21", TRCRSCTLR21},
|
||||||
|
{"trcrsctlr22", TRCRSCTLR22},
|
||||||
|
{"trcrsctlr23", TRCRSCTLR23},
|
||||||
|
{"trcrsctlr24", TRCRSCTLR24},
|
||||||
|
{"trcrsctlr25", TRCRSCTLR25},
|
||||||
|
{"trcrsctlr26", TRCRSCTLR26},
|
||||||
|
{"trcrsctlr27", TRCRSCTLR27},
|
||||||
|
{"trcrsctlr28", TRCRSCTLR28},
|
||||||
|
{"trcrsctlr29", TRCRSCTLR29},
|
||||||
|
{"trcrsctlr30", TRCRSCTLR30},
|
||||||
|
{"trcrsctlr31", TRCRSCTLR31},
|
||||||
|
{"trcssccr0", TRCSSCCR0},
|
||||||
|
{"trcssccr1", TRCSSCCR1},
|
||||||
|
{"trcssccr2", TRCSSCCR2},
|
||||||
|
{"trcssccr3", TRCSSCCR3},
|
||||||
|
{"trcssccr4", TRCSSCCR4},
|
||||||
|
{"trcssccr5", TRCSSCCR5},
|
||||||
|
{"trcssccr6", TRCSSCCR6},
|
||||||
|
{"trcssccr7", TRCSSCCR7},
|
||||||
|
{"trcsscsr0", TRCSSCSR0},
|
||||||
|
{"trcsscsr1", TRCSSCSR1},
|
||||||
|
{"trcsscsr2", TRCSSCSR2},
|
||||||
|
{"trcsscsr3", TRCSSCSR3},
|
||||||
|
{"trcsscsr4", TRCSSCSR4},
|
||||||
|
{"trcsscsr5", TRCSSCSR5},
|
||||||
|
{"trcsscsr6", TRCSSCSR6},
|
||||||
|
{"trcsscsr7", TRCSSCSR7},
|
||||||
|
{"trcsspcicr0", TRCSSPCICR0},
|
||||||
|
{"trcsspcicr1", TRCSSPCICR1},
|
||||||
|
{"trcsspcicr2", TRCSSPCICR2},
|
||||||
|
{"trcsspcicr3", TRCSSPCICR3},
|
||||||
|
{"trcsspcicr4", TRCSSPCICR4},
|
||||||
|
{"trcsspcicr5", TRCSSPCICR5},
|
||||||
|
{"trcsspcicr6", TRCSSPCICR6},
|
||||||
|
{"trcsspcicr7", TRCSSPCICR7},
|
||||||
|
{"trcpdcr", TRCPDCR},
|
||||||
|
{"trcacvr0", TRCACVR0},
|
||||||
|
{"trcacvr1", TRCACVR1},
|
||||||
|
{"trcacvr2", TRCACVR2},
|
||||||
|
{"trcacvr3", TRCACVR3},
|
||||||
|
{"trcacvr4", TRCACVR4},
|
||||||
|
{"trcacvr5", TRCACVR5},
|
||||||
|
{"trcacvr6", TRCACVR6},
|
||||||
|
{"trcacvr7", TRCACVR7},
|
||||||
|
{"trcacvr8", TRCACVR8},
|
||||||
|
{"trcacvr9", TRCACVR9},
|
||||||
|
{"trcacvr10", TRCACVR10},
|
||||||
|
{"trcacvr11", TRCACVR11},
|
||||||
|
{"trcacvr12", TRCACVR12},
|
||||||
|
{"trcacvr13", TRCACVR13},
|
||||||
|
{"trcacvr14", TRCACVR14},
|
||||||
|
{"trcacvr15", TRCACVR15},
|
||||||
|
{"trcacatr0", TRCACATR0},
|
||||||
|
{"trcacatr1", TRCACATR1},
|
||||||
|
{"trcacatr2", TRCACATR2},
|
||||||
|
{"trcacatr3", TRCACATR3},
|
||||||
|
{"trcacatr4", TRCACATR4},
|
||||||
|
{"trcacatr5", TRCACATR5},
|
||||||
|
{"trcacatr6", TRCACATR6},
|
||||||
|
{"trcacatr7", TRCACATR7},
|
||||||
|
{"trcacatr8", TRCACATR8},
|
||||||
|
{"trcacatr9", TRCACATR9},
|
||||||
|
{"trcacatr10", TRCACATR10},
|
||||||
|
{"trcacatr11", TRCACATR11},
|
||||||
|
{"trcacatr12", TRCACATR12},
|
||||||
|
{"trcacatr13", TRCACATR13},
|
||||||
|
{"trcacatr14", TRCACATR14},
|
||||||
|
{"trcacatr15", TRCACATR15},
|
||||||
|
{"trcdvcvr0", TRCDVCVR0},
|
||||||
|
{"trcdvcvr1", TRCDVCVR1},
|
||||||
|
{"trcdvcvr2", TRCDVCVR2},
|
||||||
|
{"trcdvcvr3", TRCDVCVR3},
|
||||||
|
{"trcdvcvr4", TRCDVCVR4},
|
||||||
|
{"trcdvcvr5", TRCDVCVR5},
|
||||||
|
{"trcdvcvr6", TRCDVCVR6},
|
||||||
|
{"trcdvcvr7", TRCDVCVR7},
|
||||||
|
{"trcdvcmr0", TRCDVCMR0},
|
||||||
|
{"trcdvcmr1", TRCDVCMR1},
|
||||||
|
{"trcdvcmr2", TRCDVCMR2},
|
||||||
|
{"trcdvcmr3", TRCDVCMR3},
|
||||||
|
{"trcdvcmr4", TRCDVCMR4},
|
||||||
|
{"trcdvcmr5", TRCDVCMR5},
|
||||||
|
{"trcdvcmr6", TRCDVCMR6},
|
||||||
|
{"trcdvcmr7", TRCDVCMR7},
|
||||||
|
{"trccidcvr0", TRCCIDCVR0},
|
||||||
|
{"trccidcvr1", TRCCIDCVR1},
|
||||||
|
{"trccidcvr2", TRCCIDCVR2},
|
||||||
|
{"trccidcvr3", TRCCIDCVR3},
|
||||||
|
{"trccidcvr4", TRCCIDCVR4},
|
||||||
|
{"trccidcvr5", TRCCIDCVR5},
|
||||||
|
{"trccidcvr6", TRCCIDCVR6},
|
||||||
|
{"trccidcvr7", TRCCIDCVR7},
|
||||||
|
{"trcvmidcvr0", TRCVMIDCVR0},
|
||||||
|
{"trcvmidcvr1", TRCVMIDCVR1},
|
||||||
|
{"trcvmidcvr2", TRCVMIDCVR2},
|
||||||
|
{"trcvmidcvr3", TRCVMIDCVR3},
|
||||||
|
{"trcvmidcvr4", TRCVMIDCVR4},
|
||||||
|
{"trcvmidcvr5", TRCVMIDCVR5},
|
||||||
|
{"trcvmidcvr6", TRCVMIDCVR6},
|
||||||
|
{"trcvmidcvr7", TRCVMIDCVR7},
|
||||||
|
{"trccidcctlr0", TRCCIDCCTLR0},
|
||||||
|
{"trccidcctlr1", TRCCIDCCTLR1},
|
||||||
|
{"trcvmidcctlr0", TRCVMIDCCTLR0},
|
||||||
|
{"trcvmidcctlr1", TRCVMIDCCTLR1},
|
||||||
|
{"trcitctrl", TRCITCTRL},
|
||||||
|
{"trcclaimset", TRCCLAIMSET},
|
||||||
|
{"trcclaimclr", TRCCLAIMCLR},
|
||||||
|
|
||||||
// GICv3 registers
|
// GICv3 registers
|
||||||
{"icc_bpr1_el1", ICC_BPR1_EL1},
|
{"icc_bpr1_el1", ICC_BPR1_EL1},
|
||||||
{"icc_bpr0_el1", ICC_BPR0_EL1},
|
{"icc_bpr0_el1", ICC_BPR0_EL1},
|
||||||
|
|||||||
@ -356,6 +356,44 @@ namespace A64SysReg {
|
|||||||
CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
|
CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
|
||||||
CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
|
CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
|
||||||
|
|
||||||
|
// Trace registers
|
||||||
|
TRCSTATR = 0x8818, // 10 001 0000 0011 000
|
||||||
|
TRCIDR8 = 0x8806, // 10 001 0000 0000 110
|
||||||
|
TRCIDR9 = 0x880e, // 10 001 0000 0001 110
|
||||||
|
TRCIDR10 = 0x8816, // 10 001 0000 0010 110
|
||||||
|
TRCIDR11 = 0x881e, // 10 001 0000 0011 110
|
||||||
|
TRCIDR12 = 0x8826, // 10 001 0000 0100 110
|
||||||
|
TRCIDR13 = 0x882e, // 10 001 0000 0101 110
|
||||||
|
TRCIDR0 = 0x8847, // 10 001 0000 1000 111
|
||||||
|
TRCIDR1 = 0x884f, // 10 001 0000 1001 111
|
||||||
|
TRCIDR2 = 0x8857, // 10 001 0000 1010 111
|
||||||
|
TRCIDR3 = 0x885f, // 10 001 0000 1011 111
|
||||||
|
TRCIDR4 = 0x8867, // 10 001 0000 1100 111
|
||||||
|
TRCIDR5 = 0x886f, // 10 001 0000 1101 111
|
||||||
|
TRCIDR6 = 0x8877, // 10 001 0000 1110 111
|
||||||
|
TRCIDR7 = 0x887f, // 10 001 0000 1111 111
|
||||||
|
TRCOSLSR = 0x888c, // 10 001 0001 0001 100
|
||||||
|
TRCPDSR = 0x88ac, // 10 001 0001 0101 100
|
||||||
|
TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
|
||||||
|
TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
|
||||||
|
TRCLSR = 0x8bee, // 10 001 0111 1101 110
|
||||||
|
TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
|
||||||
|
TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
|
||||||
|
TRCDEVID = 0x8b97, // 10 001 0111 0010 111
|
||||||
|
TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
|
||||||
|
TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
|
||||||
|
TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
|
||||||
|
TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
|
||||||
|
TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
|
||||||
|
TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
|
||||||
|
TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
|
||||||
|
TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
|
||||||
|
TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
|
||||||
|
TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
|
||||||
|
TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
|
||||||
|
TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
|
||||||
|
TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
|
||||||
|
|
||||||
// GICv3 registers
|
// GICv3 registers
|
||||||
ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
|
ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
|
||||||
ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
|
ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
|
||||||
@ -372,6 +410,10 @@ namespace A64SysReg {
|
|||||||
OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
|
OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
|
||||||
PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
|
PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
|
||||||
|
|
||||||
|
// Trace Registers
|
||||||
|
TRCOSLAR = 0x8884, // 10 001 0001 0000 100
|
||||||
|
TRCLAR = 0x8be6, // 10 001 0111 1100 110
|
||||||
|
|
||||||
// GICv3 registers
|
// GICv3 registers
|
||||||
ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
|
ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
|
||||||
ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
|
ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
|
||||||
@ -636,6 +678,180 @@ namespace A64SysReg {
|
|||||||
PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
|
PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
|
||||||
PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
|
PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
|
||||||
|
|
||||||
|
// Trace registers
|
||||||
|
TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
|
||||||
|
TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
|
||||||
|
TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
|
||||||
|
TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
|
||||||
|
TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
|
||||||
|
TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
|
||||||
|
TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
|
||||||
|
TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
|
||||||
|
TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
|
||||||
|
TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
|
||||||
|
TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
|
||||||
|
TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
|
||||||
|
TRCQCTLR = 0x8809, // 10 001 0000 0001 001
|
||||||
|
TRCVICTLR = 0x8802, // 10 001 0000 0000 010
|
||||||
|
TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
|
||||||
|
TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
|
||||||
|
TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
|
||||||
|
TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
|
||||||
|
TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
|
||||||
|
TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
|
||||||
|
TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
|
||||||
|
TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
|
||||||
|
TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
|
||||||
|
TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
|
||||||
|
TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
|
||||||
|
TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
|
||||||
|
TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
|
||||||
|
TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
|
||||||
|
TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
|
||||||
|
TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
|
||||||
|
TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
|
||||||
|
TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
|
||||||
|
TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
|
||||||
|
TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
|
||||||
|
TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
|
||||||
|
TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
|
||||||
|
TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
|
||||||
|
TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
|
||||||
|
TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
|
||||||
|
TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
|
||||||
|
TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
|
||||||
|
TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
|
||||||
|
TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
|
||||||
|
TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
|
||||||
|
TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
|
||||||
|
TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
|
||||||
|
TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
|
||||||
|
TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
|
||||||
|
TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
|
||||||
|
TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
|
||||||
|
TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
|
||||||
|
TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
|
||||||
|
TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
|
||||||
|
TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
|
||||||
|
TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
|
||||||
|
TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
|
||||||
|
TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
|
||||||
|
TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
|
||||||
|
TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
|
||||||
|
TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
|
||||||
|
TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
|
||||||
|
TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
|
||||||
|
TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
|
||||||
|
TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
|
||||||
|
TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
|
||||||
|
TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
|
||||||
|
TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
|
||||||
|
TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
|
||||||
|
TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
|
||||||
|
TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
|
||||||
|
TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
|
||||||
|
TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
|
||||||
|
TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
|
||||||
|
TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
|
||||||
|
TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
|
||||||
|
TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
|
||||||
|
TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
|
||||||
|
TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
|
||||||
|
TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
|
||||||
|
TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
|
||||||
|
TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
|
||||||
|
TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
|
||||||
|
TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
|
||||||
|
TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
|
||||||
|
TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
|
||||||
|
TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
|
||||||
|
TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
|
||||||
|
TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
|
||||||
|
TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
|
||||||
|
TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
|
||||||
|
TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
|
||||||
|
TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
|
||||||
|
TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
|
||||||
|
TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
|
||||||
|
TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
|
||||||
|
TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
|
||||||
|
TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
|
||||||
|
TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
|
||||||
|
TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
|
||||||
|
TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
|
||||||
|
TRCPDCR = 0x88a4, // 10 001 0001 0100 100
|
||||||
|
TRCACVR0 = 0x8900, // 10 001 0010 0000 000
|
||||||
|
TRCACVR1 = 0x8910, // 10 001 0010 0010 000
|
||||||
|
TRCACVR2 = 0x8920, // 10 001 0010 0100 000
|
||||||
|
TRCACVR3 = 0x8930, // 10 001 0010 0110 000
|
||||||
|
TRCACVR4 = 0x8940, // 10 001 0010 1000 000
|
||||||
|
TRCACVR5 = 0x8950, // 10 001 0010 1010 000
|
||||||
|
TRCACVR6 = 0x8960, // 10 001 0010 1100 000
|
||||||
|
TRCACVR7 = 0x8970, // 10 001 0010 1110 000
|
||||||
|
TRCACVR8 = 0x8901, // 10 001 0010 0000 001
|
||||||
|
TRCACVR9 = 0x8911, // 10 001 0010 0010 001
|
||||||
|
TRCACVR10 = 0x8921, // 10 001 0010 0100 001
|
||||||
|
TRCACVR11 = 0x8931, // 10 001 0010 0110 001
|
||||||
|
TRCACVR12 = 0x8941, // 10 001 0010 1000 001
|
||||||
|
TRCACVR13 = 0x8951, // 10 001 0010 1010 001
|
||||||
|
TRCACVR14 = 0x8961, // 10 001 0010 1100 001
|
||||||
|
TRCACVR15 = 0x8971, // 10 001 0010 1110 001
|
||||||
|
TRCACATR0 = 0x8902, // 10 001 0010 0000 010
|
||||||
|
TRCACATR1 = 0x8912, // 10 001 0010 0010 010
|
||||||
|
TRCACATR2 = 0x8922, // 10 001 0010 0100 010
|
||||||
|
TRCACATR3 = 0x8932, // 10 001 0010 0110 010
|
||||||
|
TRCACATR4 = 0x8942, // 10 001 0010 1000 010
|
||||||
|
TRCACATR5 = 0x8952, // 10 001 0010 1010 010
|
||||||
|
TRCACATR6 = 0x8962, // 10 001 0010 1100 010
|
||||||
|
TRCACATR7 = 0x8972, // 10 001 0010 1110 010
|
||||||
|
TRCACATR8 = 0x8903, // 10 001 0010 0000 011
|
||||||
|
TRCACATR9 = 0x8913, // 10 001 0010 0010 011
|
||||||
|
TRCACATR10 = 0x8923, // 10 001 0010 0100 011
|
||||||
|
TRCACATR11 = 0x8933, // 10 001 0010 0110 011
|
||||||
|
TRCACATR12 = 0x8943, // 10 001 0010 1000 011
|
||||||
|
TRCACATR13 = 0x8953, // 10 001 0010 1010 011
|
||||||
|
TRCACATR14 = 0x8963, // 10 001 0010 1100 011
|
||||||
|
TRCACATR15 = 0x8973, // 10 001 0010 1110 011
|
||||||
|
TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
|
||||||
|
TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
|
||||||
|
TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
|
||||||
|
TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
|
||||||
|
TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
|
||||||
|
TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
|
||||||
|
TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
|
||||||
|
TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
|
||||||
|
TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
|
||||||
|
TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
|
||||||
|
TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
|
||||||
|
TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
|
||||||
|
TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
|
||||||
|
TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
|
||||||
|
TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
|
||||||
|
TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
|
||||||
|
TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
|
||||||
|
TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
|
||||||
|
TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
|
||||||
|
TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
|
||||||
|
TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
|
||||||
|
TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
|
||||||
|
TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
|
||||||
|
TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
|
||||||
|
TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
|
||||||
|
TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
|
||||||
|
TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
|
||||||
|
TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
|
||||||
|
TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
|
||||||
|
TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
|
||||||
|
TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
|
||||||
|
TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
|
||||||
|
TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
|
||||||
|
TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
|
||||||
|
TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
|
||||||
|
TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
|
||||||
|
TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
|
||||||
|
TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
|
||||||
|
TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
|
||||||
|
|
||||||
// GICv3 registers
|
// GICv3 registers
|
||||||
ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
|
ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
|
||||||
ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
|
ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
|
||||||
|
|||||||
156
test/MC/AArch64/trace-regs-diagnostics.s
Normal file
156
test/MC/AArch64/trace-regs-diagnostics.s
Normal file
@ -0,0 +1,156 @@
|
|||||||
|
// RUN: llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
|
||||||
|
// Write-only
|
||||||
|
mrs x12, trcoslar
|
||||||
|
mrs x10, trclar
|
||||||
|
// CHECK: error: expected readable system register
|
||||||
|
// CHECK-NEXT: mrs x12, trcoslar
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected readable system register
|
||||||
|
// CHECK-NEXT: mrs x10, trclar
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
|
||||||
|
// Read-only
|
||||||
|
msr trcstatr, x0
|
||||||
|
msr trcidr8, x13
|
||||||
|
msr trcidr9, x25
|
||||||
|
msr trcidr10, x2
|
||||||
|
msr trcidr11, x19
|
||||||
|
msr trcidr12, x15
|
||||||
|
msr trcidr13, x24
|
||||||
|
msr trcidr0, x20
|
||||||
|
msr trcidr1, x5
|
||||||
|
msr trcidr2, x18
|
||||||
|
msr trcidr3, x10
|
||||||
|
msr trcidr4, x1
|
||||||
|
msr trcidr5, x10
|
||||||
|
msr trcidr6, x4
|
||||||
|
msr trcidr7, x0
|
||||||
|
msr trcoslsr, x23
|
||||||
|
msr trcpdsr, x21
|
||||||
|
msr trcdevaff0, x4
|
||||||
|
msr trcdevaff1, x17
|
||||||
|
msr trclsr, x18
|
||||||
|
msr trcauthstatus, x10
|
||||||
|
msr trcdevarch, x8
|
||||||
|
msr trcdevid, x11
|
||||||
|
msr trcdevtype, x1
|
||||||
|
msr trcpidr4, x2
|
||||||
|
msr trcpidr5, x7
|
||||||
|
msr trcpidr6, x17
|
||||||
|
msr trcpidr7, x5
|
||||||
|
msr trcpidr0, x0
|
||||||
|
msr trcpidr1, x16
|
||||||
|
msr trcpidr2, x29
|
||||||
|
msr trcpidr3, x1
|
||||||
|
msr trccidr0, x27
|
||||||
|
msr trccidr1, x1
|
||||||
|
msr trccidr2, x24
|
||||||
|
msr trccidr3, x8
|
||||||
|
// CHECK: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcstatr, x0
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr8, x13
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr9, x25
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr10, x2
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr11, x19
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr12, x15
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr13, x24
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr0, x20
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr1, x5
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr2, x18
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr3, x10
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr4, x1
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr5, x10
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr6, x4
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcidr7, x0
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcoslsr, x23
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcpdsr, x21
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcdevaff0, x4
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcdevaff1, x17
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trclsr, x18
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcauthstatus, x10
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcdevarch, x8
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcdevid, x11
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcdevtype, x1
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcpidr4, x2
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcpidr5, x7
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcpidr6, x17
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcpidr7, x5
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcpidr0, x0
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcpidr1, x16
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcpidr2, x29
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trcpidr3, x1
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trccidr0, x27
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trccidr1, x1
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trccidr2, x24
|
||||||
|
// CHECK-NEXT: ^
|
||||||
|
// CHECK-NEXT: error: expected writable system register or pstate
|
||||||
|
// CHECK-NEXT: msr trccidr3, x8
|
||||||
|
// CHECK-NEXT: ^
|
||||||
766
test/MC/AArch64/trace-regs.s
Normal file
766
test/MC/AArch64/trace-regs.s
Normal file
@ -0,0 +1,766 @@
|
|||||||
|
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
|
||||||
|
mrs x8, trcstatr
|
||||||
|
mrs x9, trcidr8
|
||||||
|
mrs x11, trcidr9
|
||||||
|
mrs x25, trcidr10
|
||||||
|
mrs x7, trcidr11
|
||||||
|
mrs x7, trcidr12
|
||||||
|
mrs x6, trcidr13
|
||||||
|
mrs x27, trcidr0
|
||||||
|
mrs x29, trcidr1
|
||||||
|
mrs x4, trcidr2
|
||||||
|
mrs x8, trcidr3
|
||||||
|
mrs x15, trcidr4
|
||||||
|
mrs x20, trcidr5
|
||||||
|
mrs x6, trcidr6
|
||||||
|
mrs x6, trcidr7
|
||||||
|
mrs x24, trcoslsr
|
||||||
|
mrs x18, trcpdsr
|
||||||
|
mrs x28, trcdevaff0
|
||||||
|
mrs x5, trcdevaff1
|
||||||
|
mrs x5, trclsr
|
||||||
|
mrs x11, trcauthstatus
|
||||||
|
mrs x13, trcdevarch
|
||||||
|
mrs x18, trcdevid
|
||||||
|
mrs x22, trcdevtype
|
||||||
|
mrs x14, trcpidr4
|
||||||
|
mrs x5, trcpidr5
|
||||||
|
mrs x5, trcpidr6
|
||||||
|
mrs x9, trcpidr7
|
||||||
|
mrs x15, trcpidr0
|
||||||
|
mrs x6, trcpidr1
|
||||||
|
mrs x11, trcpidr2
|
||||||
|
mrs x20, trcpidr3
|
||||||
|
mrs x17, trccidr0
|
||||||
|
mrs x2, trccidr1
|
||||||
|
mrs x20, trccidr2
|
||||||
|
mrs x4, trccidr3
|
||||||
|
mrs x11, trcprgctlr
|
||||||
|
mrs x23, trcprocselr
|
||||||
|
mrs x13, trcconfigr
|
||||||
|
mrs x23, trcauxctlr
|
||||||
|
mrs x9, trceventctl0r
|
||||||
|
mrs x16, trceventctl1r
|
||||||
|
mrs x4, trcstallctlr
|
||||||
|
mrs x14, trctsctlr
|
||||||
|
mrs x24, trcsyncpr
|
||||||
|
mrs x28, trcccctlr
|
||||||
|
mrs x15, trcbbctlr
|
||||||
|
mrs x1, trctraceidr
|
||||||
|
mrs x20, trcqctlr
|
||||||
|
mrs x2, trcvictlr
|
||||||
|
mrs x12, trcviiectlr
|
||||||
|
mrs x16, trcvissctlr
|
||||||
|
mrs x8, trcvipcssctlr
|
||||||
|
mrs x27, trcvdctlr
|
||||||
|
mrs x9, trcvdsacctlr
|
||||||
|
mrs x0, trcvdarcctlr
|
||||||
|
mrs x13, trcseqevr0
|
||||||
|
mrs x11, trcseqevr1
|
||||||
|
mrs x26, trcseqevr2
|
||||||
|
mrs x14, trcseqrstevr
|
||||||
|
mrs x4, trcseqstr
|
||||||
|
mrs x17, trcextinselr
|
||||||
|
mrs x21, trccntrldvr0
|
||||||
|
mrs x10, trccntrldvr1
|
||||||
|
mrs x20, trccntrldvr2
|
||||||
|
mrs x5, trccntrldvr3
|
||||||
|
mrs x17, trccntctlr0
|
||||||
|
mrs x1, trccntctlr1
|
||||||
|
mrs x17, trccntctlr2
|
||||||
|
mrs x6, trccntctlr3
|
||||||
|
mrs x28, trccntvr0
|
||||||
|
mrs x23, trccntvr1
|
||||||
|
mrs x9, trccntvr2
|
||||||
|
mrs x6, trccntvr3
|
||||||
|
mrs x24, trcimspec0
|
||||||
|
mrs x24, trcimspec1
|
||||||
|
mrs x15, trcimspec2
|
||||||
|
mrs x10, trcimspec3
|
||||||
|
mrs x29, trcimspec4
|
||||||
|
mrs x18, trcimspec5
|
||||||
|
mrs x29, trcimspec6
|
||||||
|
mrs x2, trcimspec7
|
||||||
|
mrs x8, trcrsctlr2
|
||||||
|
mrs x0, trcrsctlr3
|
||||||
|
mrs x12, trcrsctlr4
|
||||||
|
mrs x26, trcrsctlr5
|
||||||
|
mrs x29, trcrsctlr6
|
||||||
|
mrs x17, trcrsctlr7
|
||||||
|
mrs x0, trcrsctlr8
|
||||||
|
mrs x1, trcrsctlr9
|
||||||
|
mrs x17, trcrsctlr10
|
||||||
|
mrs x21, trcrsctlr11
|
||||||
|
mrs x1, trcrsctlr12
|
||||||
|
mrs x8, trcrsctlr13
|
||||||
|
mrs x24, trcrsctlr14
|
||||||
|
mrs x0, trcrsctlr15
|
||||||
|
mrs x2, trcrsctlr16
|
||||||
|
mrs x29, trcrsctlr17
|
||||||
|
mrs x22, trcrsctlr18
|
||||||
|
mrs x6, trcrsctlr19
|
||||||
|
mrs x26, trcrsctlr20
|
||||||
|
mrs x26, trcrsctlr21
|
||||||
|
mrs x4, trcrsctlr22
|
||||||
|
mrs x12, trcrsctlr23
|
||||||
|
mrs x1, trcrsctlr24
|
||||||
|
mrs x0, trcrsctlr25
|
||||||
|
mrs x17, trcrsctlr26
|
||||||
|
mrs x8, trcrsctlr27
|
||||||
|
mrs x10, trcrsctlr28
|
||||||
|
mrs x25, trcrsctlr29
|
||||||
|
mrs x12, trcrsctlr30
|
||||||
|
mrs x11, trcrsctlr31
|
||||||
|
mrs x18, trcssccr0
|
||||||
|
mrs x12, trcssccr1
|
||||||
|
mrs x3, trcssccr2
|
||||||
|
mrs x2, trcssccr3
|
||||||
|
mrs x21, trcssccr4
|
||||||
|
mrs x10, trcssccr5
|
||||||
|
mrs x22, trcssccr6
|
||||||
|
mrs x23, trcssccr7
|
||||||
|
mrs x23, trcsscsr0
|
||||||
|
mrs x19, trcsscsr1
|
||||||
|
mrs x25, trcsscsr2
|
||||||
|
mrs x17, trcsscsr3
|
||||||
|
mrs x19, trcsscsr4
|
||||||
|
mrs x11, trcsscsr5
|
||||||
|
mrs x5, trcsscsr6
|
||||||
|
mrs x9, trcsscsr7
|
||||||
|
mrs x1, trcsspcicr0
|
||||||
|
mrs x12, trcsspcicr1
|
||||||
|
mrs x21, trcsspcicr2
|
||||||
|
mrs x11, trcsspcicr3
|
||||||
|
mrs x3, trcsspcicr4
|
||||||
|
mrs x9, trcsspcicr5
|
||||||
|
mrs x5, trcsspcicr6
|
||||||
|
mrs x2, trcsspcicr7
|
||||||
|
mrs x26, trcpdcr
|
||||||
|
mrs x8, trcacvr0
|
||||||
|
mrs x15, trcacvr1
|
||||||
|
mrs x19, trcacvr2
|
||||||
|
mrs x8, trcacvr3
|
||||||
|
mrs x28, trcacvr4
|
||||||
|
mrs x3, trcacvr5
|
||||||
|
mrs x25, trcacvr6
|
||||||
|
mrs x24, trcacvr7
|
||||||
|
mrs x6, trcacvr8
|
||||||
|
mrs x3, trcacvr9
|
||||||
|
mrs x24, trcacvr10
|
||||||
|
mrs x3, trcacvr11
|
||||||
|
mrs x12, trcacvr12
|
||||||
|
mrs x9, trcacvr13
|
||||||
|
mrs x14, trcacvr14
|
||||||
|
mrs x3, trcacvr15
|
||||||
|
mrs x21, trcacatr0
|
||||||
|
mrs x26, trcacatr1
|
||||||
|
mrs x8, trcacatr2
|
||||||
|
mrs x22, trcacatr3
|
||||||
|
mrs x6, trcacatr4
|
||||||
|
mrs x29, trcacatr5
|
||||||
|
mrs x5, trcacatr6
|
||||||
|
mrs x18, trcacatr7
|
||||||
|
mrs x2, trcacatr8
|
||||||
|
mrs x19, trcacatr9
|
||||||
|
mrs x13, trcacatr10
|
||||||
|
mrs x25, trcacatr11
|
||||||
|
mrs x18, trcacatr12
|
||||||
|
mrs x29, trcacatr13
|
||||||
|
mrs x9, trcacatr14
|
||||||
|
mrs x18, trcacatr15
|
||||||
|
mrs x29, trcdvcvr0
|
||||||
|
mrs x15, trcdvcvr1
|
||||||
|
mrs x15, trcdvcvr2
|
||||||
|
mrs x15, trcdvcvr3
|
||||||
|
mrs x19, trcdvcvr4
|
||||||
|
mrs x22, trcdvcvr5
|
||||||
|
mrs x27, trcdvcvr6
|
||||||
|
mrs x1, trcdvcvr7
|
||||||
|
mrs x29, trcdvcmr0
|
||||||
|
mrs x9, trcdvcmr1
|
||||||
|
mrs x1, trcdvcmr2
|
||||||
|
mrs x2, trcdvcmr3
|
||||||
|
mrs x5, trcdvcmr4
|
||||||
|
mrs x21, trcdvcmr5
|
||||||
|
mrs x5, trcdvcmr6
|
||||||
|
mrs x1, trcdvcmr7
|
||||||
|
mrs x21, trccidcvr0
|
||||||
|
mrs x24, trccidcvr1
|
||||||
|
mrs x24, trccidcvr2
|
||||||
|
mrs x12, trccidcvr3
|
||||||
|
mrs x10, trccidcvr4
|
||||||
|
mrs x9, trccidcvr5
|
||||||
|
mrs x6, trccidcvr6
|
||||||
|
mrs x20, trccidcvr7
|
||||||
|
mrs x20, trcvmidcvr0
|
||||||
|
mrs x20, trcvmidcvr1
|
||||||
|
mrs x26, trcvmidcvr2
|
||||||
|
mrs x1, trcvmidcvr3
|
||||||
|
mrs x14, trcvmidcvr4
|
||||||
|
mrs x27, trcvmidcvr5
|
||||||
|
mrs x29, trcvmidcvr6
|
||||||
|
mrs x17, trcvmidcvr7
|
||||||
|
mrs x10, trccidcctlr0
|
||||||
|
mrs x4, trccidcctlr1
|
||||||
|
mrs x9, trcvmidcctlr0
|
||||||
|
mrs x11, trcvmidcctlr1
|
||||||
|
mrs x22, trcitctrl
|
||||||
|
mrs x23, trcclaimset
|
||||||
|
mrs x14, trcclaimclr
|
||||||
|
// CHECK: mrs x8, trcstatr // encoding: [0x08,0x03,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trcidr8 // encoding: [0xc9,0x00,0x31,0xd5]
|
||||||
|
// CHECK: mrs x11, trcidr9 // encoding: [0xcb,0x01,0x31,0xd5]
|
||||||
|
// CHECK: mrs x25, trcidr10 // encoding: [0xd9,0x02,0x31,0xd5]
|
||||||
|
// CHECK: mrs x7, trcidr11 // encoding: [0xc7,0x03,0x31,0xd5]
|
||||||
|
// CHECK: mrs x7, trcidr12 // encoding: [0xc7,0x04,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trcidr13 // encoding: [0xc6,0x05,0x31,0xd5]
|
||||||
|
// CHECK: mrs x27, trcidr0 // encoding: [0xfb,0x08,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcidr1 // encoding: [0xfd,0x09,0x31,0xd5]
|
||||||
|
// CHECK: mrs x4, trcidr2 // encoding: [0xe4,0x0a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x8, trcidr3 // encoding: [0xe8,0x0b,0x31,0xd5]
|
||||||
|
// CHECK: mrs x15, trcidr4 // encoding: [0xef,0x0c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x20, trcidr5 // encoding: [0xf4,0x0d,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trcidr6 // encoding: [0xe6,0x0e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trcidr7 // encoding: [0xe6,0x0f,0x31,0xd5]
|
||||||
|
// CHECK: mrs x24, trcoslsr // encoding: [0x98,0x11,0x31,0xd5]
|
||||||
|
// CHECK: mrs x18, trcpdsr // encoding: [0x92,0x15,0x31,0xd5]
|
||||||
|
// CHECK: mrs x28, trcdevaff0 // encoding: [0xdc,0x7a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trcdevaff1 // encoding: [0xc5,0x7b,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trclsr // encoding: [0xc5,0x7d,0x31,0xd5]
|
||||||
|
// CHECK: mrs x11, trcauthstatus // encoding: [0xcb,0x7e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x13, trcdevarch // encoding: [0xcd,0x7f,0x31,0xd5]
|
||||||
|
// CHECK: mrs x18, trcdevid // encoding: [0xf2,0x72,0x31,0xd5]
|
||||||
|
// CHECK: mrs x22, trcdevtype // encoding: [0xf6,0x73,0x31,0xd5]
|
||||||
|
// CHECK: mrs x14, trcpidr4 // encoding: [0xee,0x74,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trcpidr5 // encoding: [0xe5,0x75,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trcpidr6 // encoding: [0xe5,0x76,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trcpidr7 // encoding: [0xe9,0x77,0x31,0xd5]
|
||||||
|
// CHECK: mrs x15, trcpidr0 // encoding: [0xef,0x78,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trcpidr1 // encoding: [0xe6,0x79,0x31,0xd5]
|
||||||
|
// CHECK: mrs x11, trcpidr2 // encoding: [0xeb,0x7a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x20, trcpidr3 // encoding: [0xf4,0x7b,0x31,0xd5]
|
||||||
|
// CHECK: mrs x17, trccidr0 // encoding: [0xf1,0x7c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x2, trccidr1 // encoding: [0xe2,0x7d,0x31,0xd5]
|
||||||
|
// CHECK: mrs x20, trccidr2 // encoding: [0xf4,0x7e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x4, trccidr3 // encoding: [0xe4,0x7f,0x31,0xd5]
|
||||||
|
// CHECK: mrs x11, trcprgctlr // encoding: [0x0b,0x01,0x31,0xd5]
|
||||||
|
// CHECK: mrs x23, trcprocselr // encoding: [0x17,0x02,0x31,0xd5]
|
||||||
|
// CHECK: mrs x13, trcconfigr // encoding: [0x0d,0x04,0x31,0xd5]
|
||||||
|
// CHECK: mrs x23, trcauxctlr // encoding: [0x17,0x06,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trceventctl0r // encoding: [0x09,0x08,0x31,0xd5]
|
||||||
|
// CHECK: mrs x16, trceventctl1r // encoding: [0x10,0x09,0x31,0xd5]
|
||||||
|
// CHECK: mrs x4, trcstallctlr // encoding: [0x04,0x0b,0x31,0xd5]
|
||||||
|
// CHECK: mrs x14, trctsctlr // encoding: [0x0e,0x0c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x24, trcsyncpr // encoding: [0x18,0x0d,0x31,0xd5]
|
||||||
|
// CHECK: mrs x28, trcccctlr // encoding: [0x1c,0x0e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x15, trcbbctlr // encoding: [0x0f,0x0f,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trctraceidr // encoding: [0x21,0x00,0x31,0xd5]
|
||||||
|
// CHECK: mrs x20, trcqctlr // encoding: [0x34,0x01,0x31,0xd5]
|
||||||
|
// CHECK: mrs x2, trcvictlr // encoding: [0x42,0x00,0x31,0xd5]
|
||||||
|
// CHECK: mrs x12, trcviiectlr // encoding: [0x4c,0x01,0x31,0xd5]
|
||||||
|
// CHECK: mrs x16, trcvissctlr // encoding: [0x50,0x02,0x31,0xd5]
|
||||||
|
// CHECK: mrs x8, trcvipcssctlr // encoding: [0x48,0x03,0x31,0xd5]
|
||||||
|
// CHECK: mrs x27, trcvdctlr // encoding: [0x5b,0x08,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trcvdsacctlr // encoding: [0x49,0x09,0x31,0xd5]
|
||||||
|
// CHECK: mrs x0, trcvdarcctlr // encoding: [0x40,0x0a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x13, trcseqevr0 // encoding: [0x8d,0x00,0x31,0xd5]
|
||||||
|
// CHECK: mrs x11, trcseqevr1 // encoding: [0x8b,0x01,0x31,0xd5]
|
||||||
|
// CHECK: mrs x26, trcseqevr2 // encoding: [0x9a,0x02,0x31,0xd5]
|
||||||
|
// CHECK: mrs x14, trcseqrstevr // encoding: [0x8e,0x06,0x31,0xd5]
|
||||||
|
// CHECK: mrs x4, trcseqstr // encoding: [0x84,0x07,0x31,0xd5]
|
||||||
|
// CHECK: mrs x17, trcextinselr // encoding: [0x91,0x08,0x31,0xd5]
|
||||||
|
// CHECK: mrs x21, trccntrldvr0 // encoding: [0xb5,0x00,0x31,0xd5]
|
||||||
|
// CHECK: mrs x10, trccntrldvr1 // encoding: [0xaa,0x01,0x31,0xd5]
|
||||||
|
// CHECK: mrs x20, trccntrldvr2 // encoding: [0xb4,0x02,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trccntrldvr3 // encoding: [0xa5,0x03,0x31,0xd5]
|
||||||
|
// CHECK: mrs x17, trccntctlr0 // encoding: [0xb1,0x04,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trccntctlr1 // encoding: [0xa1,0x05,0x31,0xd5]
|
||||||
|
// CHECK: mrs x17, trccntctlr2 // encoding: [0xb1,0x06,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trccntctlr3 // encoding: [0xa6,0x07,0x31,0xd5]
|
||||||
|
// CHECK: mrs x28, trccntvr0 // encoding: [0xbc,0x08,0x31,0xd5]
|
||||||
|
// CHECK: mrs x23, trccntvr1 // encoding: [0xb7,0x09,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trccntvr2 // encoding: [0xa9,0x0a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trccntvr3 // encoding: [0xa6,0x0b,0x31,0xd5]
|
||||||
|
// CHECK: mrs x24, trcimspec0 // encoding: [0xf8,0x00,0x31,0xd5]
|
||||||
|
// CHECK: mrs x24, trcimspec1 // encoding: [0xf8,0x01,0x31,0xd5]
|
||||||
|
// CHECK: mrs x15, trcimspec2 // encoding: [0xef,0x02,0x31,0xd5]
|
||||||
|
// CHECK: mrs x10, trcimspec3 // encoding: [0xea,0x03,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcimspec4 // encoding: [0xfd,0x04,0x31,0xd5]
|
||||||
|
// CHECK: mrs x18, trcimspec5 // encoding: [0xf2,0x05,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcimspec6 // encoding: [0xfd,0x06,0x31,0xd5]
|
||||||
|
// CHECK: mrs x2, trcimspec7 // encoding: [0xe2,0x07,0x31,0xd5]
|
||||||
|
// CHECK: mrs x8, trcrsctlr2 // encoding: [0x08,0x12,0x31,0xd5]
|
||||||
|
// CHECK: mrs x0, trcrsctlr3 // encoding: [0x00,0x13,0x31,0xd5]
|
||||||
|
// CHECK: mrs x12, trcrsctlr4 // encoding: [0x0c,0x14,0x31,0xd5]
|
||||||
|
// CHECK: mrs x26, trcrsctlr5 // encoding: [0x1a,0x15,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcrsctlr6 // encoding: [0x1d,0x16,0x31,0xd5]
|
||||||
|
// CHECK: mrs x17, trcrsctlr7 // encoding: [0x11,0x17,0x31,0xd5]
|
||||||
|
// CHECK: mrs x0, trcrsctlr8 // encoding: [0x00,0x18,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trcrsctlr9 // encoding: [0x01,0x19,0x31,0xd5]
|
||||||
|
// CHECK: mrs x17, trcrsctlr10 // encoding: [0x11,0x1a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x21, trcrsctlr11 // encoding: [0x15,0x1b,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trcrsctlr12 // encoding: [0x01,0x1c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x8, trcrsctlr13 // encoding: [0x08,0x1d,0x31,0xd5]
|
||||||
|
// CHECK: mrs x24, trcrsctlr14 // encoding: [0x18,0x1e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x0, trcrsctlr15 // encoding: [0x00,0x1f,0x31,0xd5]
|
||||||
|
// CHECK: mrs x2, trcrsctlr16 // encoding: [0x22,0x10,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcrsctlr17 // encoding: [0x3d,0x11,0x31,0xd5]
|
||||||
|
// CHECK: mrs x22, trcrsctlr18 // encoding: [0x36,0x12,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trcrsctlr19 // encoding: [0x26,0x13,0x31,0xd5]
|
||||||
|
// CHECK: mrs x26, trcrsctlr20 // encoding: [0x3a,0x14,0x31,0xd5]
|
||||||
|
// CHECK: mrs x26, trcrsctlr21 // encoding: [0x3a,0x15,0x31,0xd5]
|
||||||
|
// CHECK: mrs x4, trcrsctlr22 // encoding: [0x24,0x16,0x31,0xd5]
|
||||||
|
// CHECK: mrs x12, trcrsctlr23 // encoding: [0x2c,0x17,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trcrsctlr24 // encoding: [0x21,0x18,0x31,0xd5]
|
||||||
|
// CHECK: mrs x0, trcrsctlr25 // encoding: [0x20,0x19,0x31,0xd5]
|
||||||
|
// CHECK: mrs x17, trcrsctlr26 // encoding: [0x31,0x1a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x8, trcrsctlr27 // encoding: [0x28,0x1b,0x31,0xd5]
|
||||||
|
// CHECK: mrs x10, trcrsctlr28 // encoding: [0x2a,0x1c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x25, trcrsctlr29 // encoding: [0x39,0x1d,0x31,0xd5]
|
||||||
|
// CHECK: mrs x12, trcrsctlr30 // encoding: [0x2c,0x1e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x11, trcrsctlr31 // encoding: [0x2b,0x1f,0x31,0xd5]
|
||||||
|
// CHECK: mrs x18, trcssccr0 // encoding: [0x52,0x10,0x31,0xd5]
|
||||||
|
// CHECK: mrs x12, trcssccr1 // encoding: [0x4c,0x11,0x31,0xd5]
|
||||||
|
// CHECK: mrs x3, trcssccr2 // encoding: [0x43,0x12,0x31,0xd5]
|
||||||
|
// CHECK: mrs x2, trcssccr3 // encoding: [0x42,0x13,0x31,0xd5]
|
||||||
|
// CHECK: mrs x21, trcssccr4 // encoding: [0x55,0x14,0x31,0xd5]
|
||||||
|
// CHECK: mrs x10, trcssccr5 // encoding: [0x4a,0x15,0x31,0xd5]
|
||||||
|
// CHECK: mrs x22, trcssccr6 // encoding: [0x56,0x16,0x31,0xd5]
|
||||||
|
// CHECK: mrs x23, trcssccr7 // encoding: [0x57,0x17,0x31,0xd5]
|
||||||
|
// CHECK: mrs x23, trcsscsr0 // encoding: [0x57,0x18,0x31,0xd5]
|
||||||
|
// CHECK: mrs x19, trcsscsr1 // encoding: [0x53,0x19,0x31,0xd5]
|
||||||
|
// CHECK: mrs x25, trcsscsr2 // encoding: [0x59,0x1a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x17, trcsscsr3 // encoding: [0x51,0x1b,0x31,0xd5]
|
||||||
|
// CHECK: mrs x19, trcsscsr4 // encoding: [0x53,0x1c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x11, trcsscsr5 // encoding: [0x4b,0x1d,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trcsscsr6 // encoding: [0x45,0x1e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trcsscsr7 // encoding: [0x49,0x1f,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trcsspcicr0 // encoding: [0x61,0x10,0x31,0xd5]
|
||||||
|
// CHECK: mrs x12, trcsspcicr1 // encoding: [0x6c,0x11,0x31,0xd5]
|
||||||
|
// CHECK: mrs x21, trcsspcicr2 // encoding: [0x75,0x12,0x31,0xd5]
|
||||||
|
// CHECK: mrs x11, trcsspcicr3 // encoding: [0x6b,0x13,0x31,0xd5]
|
||||||
|
// CHECK: mrs x3, trcsspcicr4 // encoding: [0x63,0x14,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trcsspcicr5 // encoding: [0x69,0x15,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trcsspcicr6 // encoding: [0x65,0x16,0x31,0xd5]
|
||||||
|
// CHECK: mrs x2, trcsspcicr7 // encoding: [0x62,0x17,0x31,0xd5]
|
||||||
|
// CHECK: mrs x26, trcpdcr // encoding: [0x9a,0x14,0x31,0xd5]
|
||||||
|
// CHECK: mrs x8, trcacvr0 // encoding: [0x08,0x20,0x31,0xd5]
|
||||||
|
// CHECK: mrs x15, trcacvr1 // encoding: [0x0f,0x22,0x31,0xd5]
|
||||||
|
// CHECK: mrs x19, trcacvr2 // encoding: [0x13,0x24,0x31,0xd5]
|
||||||
|
// CHECK: mrs x8, trcacvr3 // encoding: [0x08,0x26,0x31,0xd5]
|
||||||
|
// CHECK: mrs x28, trcacvr4 // encoding: [0x1c,0x28,0x31,0xd5]
|
||||||
|
// CHECK: mrs x3, trcacvr5 // encoding: [0x03,0x2a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x25, trcacvr6 // encoding: [0x19,0x2c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x24, trcacvr7 // encoding: [0x18,0x2e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trcacvr8 // encoding: [0x26,0x20,0x31,0xd5]
|
||||||
|
// CHECK: mrs x3, trcacvr9 // encoding: [0x23,0x22,0x31,0xd5]
|
||||||
|
// CHECK: mrs x24, trcacvr10 // encoding: [0x38,0x24,0x31,0xd5]
|
||||||
|
// CHECK: mrs x3, trcacvr11 // encoding: [0x23,0x26,0x31,0xd5]
|
||||||
|
// CHECK: mrs x12, trcacvr12 // encoding: [0x2c,0x28,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trcacvr13 // encoding: [0x29,0x2a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x14, trcacvr14 // encoding: [0x2e,0x2c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x3, trcacvr15 // encoding: [0x23,0x2e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x21, trcacatr0 // encoding: [0x55,0x20,0x31,0xd5]
|
||||||
|
// CHECK: mrs x26, trcacatr1 // encoding: [0x5a,0x22,0x31,0xd5]
|
||||||
|
// CHECK: mrs x8, trcacatr2 // encoding: [0x48,0x24,0x31,0xd5]
|
||||||
|
// CHECK: mrs x22, trcacatr3 // encoding: [0x56,0x26,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trcacatr4 // encoding: [0x46,0x28,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcacatr5 // encoding: [0x5d,0x2a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trcacatr6 // encoding: [0x45,0x2c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x18, trcacatr7 // encoding: [0x52,0x2e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x2, trcacatr8 // encoding: [0x62,0x20,0x31,0xd5]
|
||||||
|
// CHECK: mrs x19, trcacatr9 // encoding: [0x73,0x22,0x31,0xd5]
|
||||||
|
// CHECK: mrs x13, trcacatr10 // encoding: [0x6d,0x24,0x31,0xd5]
|
||||||
|
// CHECK: mrs x25, trcacatr11 // encoding: [0x79,0x26,0x31,0xd5]
|
||||||
|
// CHECK: mrs x18, trcacatr12 // encoding: [0x72,0x28,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcacatr13 // encoding: [0x7d,0x2a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trcacatr14 // encoding: [0x69,0x2c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x18, trcacatr15 // encoding: [0x72,0x2e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcdvcvr0 // encoding: [0x9d,0x20,0x31,0xd5]
|
||||||
|
// CHECK: mrs x15, trcdvcvr1 // encoding: [0x8f,0x24,0x31,0xd5]
|
||||||
|
// CHECK: mrs x15, trcdvcvr2 // encoding: [0x8f,0x28,0x31,0xd5]
|
||||||
|
// CHECK: mrs x15, trcdvcvr3 // encoding: [0x8f,0x2c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x19, trcdvcvr4 // encoding: [0xb3,0x20,0x31,0xd5]
|
||||||
|
// CHECK: mrs x22, trcdvcvr5 // encoding: [0xb6,0x24,0x31,0xd5]
|
||||||
|
// CHECK: mrs x27, trcdvcvr6 // encoding: [0xbb,0x28,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trcdvcvr7 // encoding: [0xa1,0x2c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcdvcmr0 // encoding: [0xdd,0x20,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trcdvcmr1 // encoding: [0xc9,0x24,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trcdvcmr2 // encoding: [0xc1,0x28,0x31,0xd5]
|
||||||
|
// CHECK: mrs x2, trcdvcmr3 // encoding: [0xc2,0x2c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trcdvcmr4 // encoding: [0xe5,0x20,0x31,0xd5]
|
||||||
|
// CHECK: mrs x21, trcdvcmr5 // encoding: [0xf5,0x24,0x31,0xd5]
|
||||||
|
// CHECK: mrs x5, trcdvcmr6 // encoding: [0xe5,0x28,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trcdvcmr7 // encoding: [0xe1,0x2c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x21, trccidcvr0 // encoding: [0x15,0x30,0x31,0xd5]
|
||||||
|
// CHECK: mrs x24, trccidcvr1 // encoding: [0x18,0x32,0x31,0xd5]
|
||||||
|
// CHECK: mrs x24, trccidcvr2 // encoding: [0x18,0x34,0x31,0xd5]
|
||||||
|
// CHECK: mrs x12, trccidcvr3 // encoding: [0x0c,0x36,0x31,0xd5]
|
||||||
|
// CHECK: mrs x10, trccidcvr4 // encoding: [0x0a,0x38,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trccidcvr5 // encoding: [0x09,0x3a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x6, trccidcvr6 // encoding: [0x06,0x3c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x20, trccidcvr7 // encoding: [0x14,0x3e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x20, trcvmidcvr0 // encoding: [0x34,0x30,0x31,0xd5]
|
||||||
|
// CHECK: mrs x20, trcvmidcvr1 // encoding: [0x34,0x32,0x31,0xd5]
|
||||||
|
// CHECK: mrs x26, trcvmidcvr2 // encoding: [0x3a,0x34,0x31,0xd5]
|
||||||
|
// CHECK: mrs x1, trcvmidcvr3 // encoding: [0x21,0x36,0x31,0xd5]
|
||||||
|
// CHECK: mrs x14, trcvmidcvr4 // encoding: [0x2e,0x38,0x31,0xd5]
|
||||||
|
// CHECK: mrs x27, trcvmidcvr5 // encoding: [0x3b,0x3a,0x31,0xd5]
|
||||||
|
// CHECK: mrs x29, trcvmidcvr6 // encoding: [0x3d,0x3c,0x31,0xd5]
|
||||||
|
// CHECK: mrs x17, trcvmidcvr7 // encoding: [0x31,0x3e,0x31,0xd5]
|
||||||
|
// CHECK: mrs x10, trccidcctlr0 // encoding: [0x4a,0x30,0x31,0xd5]
|
||||||
|
// CHECK: mrs x4, trccidcctlr1 // encoding: [0x44,0x31,0x31,0xd5]
|
||||||
|
// CHECK: mrs x9, trcvmidcctlr0 // encoding: [0x49,0x32,0x31,0xd5]
|
||||||
|
// CHECK: mrs x11, trcvmidcctlr1 // encoding: [0x4b,0x33,0x31,0xd5]
|
||||||
|
// CHECK: mrs x22, trcitctrl // encoding: [0x96,0x70,0x31,0xd5]
|
||||||
|
// CHECK: mrs x23, trcclaimset // encoding: [0xd7,0x78,0x31,0xd5]
|
||||||
|
// CHECK: mrs x14, trcclaimclr // encoding: [0xce,0x79,0x31,0xd5]
|
||||||
|
|
||||||
|
msr trcoslar, x28
|
||||||
|
msr trclar, x14
|
||||||
|
msr trcprgctlr, x10
|
||||||
|
msr trcprocselr, x27
|
||||||
|
msr trcconfigr, x24
|
||||||
|
msr trcauxctlr, x8
|
||||||
|
msr trceventctl0r, x16
|
||||||
|
msr trceventctl1r, x27
|
||||||
|
msr trcstallctlr, x26
|
||||||
|
msr trctsctlr, x0
|
||||||
|
msr trcsyncpr, x14
|
||||||
|
msr trcccctlr, x8
|
||||||
|
msr trcbbctlr, x6
|
||||||
|
msr trctraceidr, x23
|
||||||
|
msr trcqctlr, x5
|
||||||
|
msr trcvictlr, x0
|
||||||
|
msr trcviiectlr, x0
|
||||||
|
msr trcvissctlr, x1
|
||||||
|
msr trcvipcssctlr, x0
|
||||||
|
msr trcvdctlr, x7
|
||||||
|
msr trcvdsacctlr, x18
|
||||||
|
msr trcvdarcctlr, x24
|
||||||
|
msr trcseqevr0, x28
|
||||||
|
msr trcseqevr1, x21
|
||||||
|
msr trcseqevr2, x16
|
||||||
|
msr trcseqrstevr, x16
|
||||||
|
msr trcseqstr, x25
|
||||||
|
msr trcextinselr, x29
|
||||||
|
msr trccntrldvr0, x20
|
||||||
|
msr trccntrldvr1, x20
|
||||||
|
msr trccntrldvr2, x22
|
||||||
|
msr trccntrldvr3, x12
|
||||||
|
msr trccntctlr0, x20
|
||||||
|
msr trccntctlr1, x4
|
||||||
|
msr trccntctlr2, x8
|
||||||
|
msr trccntctlr3, x16
|
||||||
|
msr trccntvr0, x5
|
||||||
|
msr trccntvr1, x27
|
||||||
|
msr trccntvr2, x21
|
||||||
|
msr trccntvr3, x8
|
||||||
|
msr trcimspec0, x6
|
||||||
|
msr trcimspec1, x27
|
||||||
|
msr trcimspec2, x23
|
||||||
|
msr trcimspec3, x15
|
||||||
|
msr trcimspec4, x13
|
||||||
|
msr trcimspec5, x25
|
||||||
|
msr trcimspec6, x19
|
||||||
|
msr trcimspec7, x27
|
||||||
|
msr trcrsctlr2, x4
|
||||||
|
msr trcrsctlr3, x0
|
||||||
|
msr trcrsctlr4, x21
|
||||||
|
msr trcrsctlr5, x8
|
||||||
|
msr trcrsctlr6, x20
|
||||||
|
msr trcrsctlr7, x11
|
||||||
|
msr trcrsctlr8, x18
|
||||||
|
msr trcrsctlr9, x24
|
||||||
|
msr trcrsctlr10, x15
|
||||||
|
msr trcrsctlr11, x21
|
||||||
|
msr trcrsctlr12, x4
|
||||||
|
msr trcrsctlr13, x28
|
||||||
|
msr trcrsctlr14, x3
|
||||||
|
msr trcrsctlr15, x20
|
||||||
|
msr trcrsctlr16, x12
|
||||||
|
msr trcrsctlr17, x17
|
||||||
|
msr trcrsctlr18, x10
|
||||||
|
msr trcrsctlr19, x11
|
||||||
|
msr trcrsctlr20, x3
|
||||||
|
msr trcrsctlr21, x18
|
||||||
|
msr trcrsctlr22, x26
|
||||||
|
msr trcrsctlr23, x5
|
||||||
|
msr trcrsctlr24, x25
|
||||||
|
msr trcrsctlr25, x5
|
||||||
|
msr trcrsctlr26, x4
|
||||||
|
msr trcrsctlr27, x20
|
||||||
|
msr trcrsctlr28, x5
|
||||||
|
msr trcrsctlr29, x10
|
||||||
|
msr trcrsctlr30, x24
|
||||||
|
msr trcrsctlr31, x20
|
||||||
|
msr trcssccr0, x23
|
||||||
|
msr trcssccr1, x27
|
||||||
|
msr trcssccr2, x27
|
||||||
|
msr trcssccr3, x6
|
||||||
|
msr trcssccr4, x3
|
||||||
|
msr trcssccr5, x12
|
||||||
|
msr trcssccr6, x7
|
||||||
|
msr trcssccr7, x6
|
||||||
|
msr trcsscsr0, x20
|
||||||
|
msr trcsscsr1, x17
|
||||||
|
msr trcsscsr2, x11
|
||||||
|
msr trcsscsr3, x4
|
||||||
|
msr trcsscsr4, x14
|
||||||
|
msr trcsscsr5, x22
|
||||||
|
msr trcsscsr6, x3
|
||||||
|
msr trcsscsr7, x11
|
||||||
|
msr trcsspcicr0, x2
|
||||||
|
msr trcsspcicr1, x3
|
||||||
|
msr trcsspcicr2, x5
|
||||||
|
msr trcsspcicr3, x7
|
||||||
|
msr trcsspcicr4, x11
|
||||||
|
msr trcsspcicr5, x13
|
||||||
|
msr trcsspcicr6, x17
|
||||||
|
msr trcsspcicr7, x23
|
||||||
|
msr trcpdcr, x3
|
||||||
|
msr trcacvr0, x6
|
||||||
|
msr trcacvr1, x20
|
||||||
|
msr trcacvr2, x25
|
||||||
|
msr trcacvr3, x1
|
||||||
|
msr trcacvr4, x28
|
||||||
|
msr trcacvr5, x15
|
||||||
|
msr trcacvr6, x25
|
||||||
|
msr trcacvr7, x12
|
||||||
|
msr trcacvr8, x5
|
||||||
|
msr trcacvr9, x25
|
||||||
|
msr trcacvr10, x13
|
||||||
|
msr trcacvr11, x10
|
||||||
|
msr trcacvr12, x19
|
||||||
|
msr trcacvr13, x10
|
||||||
|
msr trcacvr14, x19
|
||||||
|
msr trcacvr15, x2
|
||||||
|
msr trcacatr0, x15
|
||||||
|
msr trcacatr1, x13
|
||||||
|
msr trcacatr2, x8
|
||||||
|
msr trcacatr3, x1
|
||||||
|
msr trcacatr4, x11
|
||||||
|
msr trcacatr5, x8
|
||||||
|
msr trcacatr6, x24
|
||||||
|
msr trcacatr7, x6
|
||||||
|
msr trcacatr8, x23
|
||||||
|
msr trcacatr9, x5
|
||||||
|
msr trcacatr10, x11
|
||||||
|
msr trcacatr11, x11
|
||||||
|
msr trcacatr12, x3
|
||||||
|
msr trcacatr13, x28
|
||||||
|
msr trcacatr14, x25
|
||||||
|
msr trcacatr15, x4
|
||||||
|
msr trcdvcvr0, x6
|
||||||
|
msr trcdvcvr1, x3
|
||||||
|
msr trcdvcvr2, x5
|
||||||
|
msr trcdvcvr3, x11
|
||||||
|
msr trcdvcvr4, x9
|
||||||
|
msr trcdvcvr5, x14
|
||||||
|
msr trcdvcvr6, x10
|
||||||
|
msr trcdvcvr7, x12
|
||||||
|
msr trcdvcmr0, x8
|
||||||
|
msr trcdvcmr1, x8
|
||||||
|
msr trcdvcmr2, x22
|
||||||
|
msr trcdvcmr3, x22
|
||||||
|
msr trcdvcmr4, x5
|
||||||
|
msr trcdvcmr5, x16
|
||||||
|
msr trcdvcmr6, x27
|
||||||
|
msr trcdvcmr7, x21
|
||||||
|
msr trccidcvr0, x8
|
||||||
|
msr trccidcvr1, x6
|
||||||
|
msr trccidcvr2, x9
|
||||||
|
msr trccidcvr3, x8
|
||||||
|
msr trccidcvr4, x3
|
||||||
|
msr trccidcvr5, x21
|
||||||
|
msr trccidcvr6, x12
|
||||||
|
msr trccidcvr7, x7
|
||||||
|
msr trcvmidcvr0, x4
|
||||||
|
msr trcvmidcvr1, x3
|
||||||
|
msr trcvmidcvr2, x9
|
||||||
|
msr trcvmidcvr3, x17
|
||||||
|
msr trcvmidcvr4, x14
|
||||||
|
msr trcvmidcvr5, x12
|
||||||
|
msr trcvmidcvr6, x10
|
||||||
|
msr trcvmidcvr7, x3
|
||||||
|
msr trccidcctlr0, x14
|
||||||
|
msr trccidcctlr1, x22
|
||||||
|
msr trcvmidcctlr0, x8
|
||||||
|
msr trcvmidcctlr1, x15
|
||||||
|
msr trcitctrl, x1
|
||||||
|
msr trcclaimset, x7
|
||||||
|
msr trcclaimclr, x29
|
||||||
|
// CHECK: msr trcoslar, x28 // encoding: [0x9c,0x10,0x11,0xd5]
|
||||||
|
// CHECK: msr trclar, x14 // encoding: [0xce,0x7c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcprgctlr, x10 // encoding: [0x0a,0x01,0x11,0xd5]
|
||||||
|
// CHECK: msr trcprocselr, x27 // encoding: [0x1b,0x02,0x11,0xd5]
|
||||||
|
// CHECK: msr trcconfigr, x24 // encoding: [0x18,0x04,0x11,0xd5]
|
||||||
|
// CHECK: msr trcauxctlr, x8 // encoding: [0x08,0x06,0x11,0xd5]
|
||||||
|
// CHECK: msr trceventctl0r, x16 // encoding: [0x10,0x08,0x11,0xd5]
|
||||||
|
// CHECK: msr trceventctl1r, x27 // encoding: [0x1b,0x09,0x11,0xd5]
|
||||||
|
// CHECK: msr trcstallctlr, x26 // encoding: [0x1a,0x0b,0x11,0xd5]
|
||||||
|
// CHECK: msr trctsctlr, x0 // encoding: [0x00,0x0c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsyncpr, x14 // encoding: [0x0e,0x0d,0x11,0xd5]
|
||||||
|
// CHECK: msr trcccctlr, x8 // encoding: [0x08,0x0e,0x11,0xd5]
|
||||||
|
// CHECK: msr trcbbctlr, x6 // encoding: [0x06,0x0f,0x11,0xd5]
|
||||||
|
// CHECK: msr trctraceidr, x23 // encoding: [0x37,0x00,0x11,0xd5]
|
||||||
|
// CHECK: msr trcqctlr, x5 // encoding: [0x25,0x01,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvictlr, x0 // encoding: [0x40,0x00,0x11,0xd5]
|
||||||
|
// CHECK: msr trcviiectlr, x0 // encoding: [0x40,0x01,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvissctlr, x1 // encoding: [0x41,0x02,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvipcssctlr, x0 // encoding: [0x40,0x03,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvdctlr, x7 // encoding: [0x47,0x08,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvdsacctlr, x18 // encoding: [0x52,0x09,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvdarcctlr, x24 // encoding: [0x58,0x0a,0x11,0xd5]
|
||||||
|
// CHECK: msr trcseqevr0, x28 // encoding: [0x9c,0x00,0x11,0xd5]
|
||||||
|
// CHECK: msr trcseqevr1, x21 // encoding: [0x95,0x01,0x11,0xd5]
|
||||||
|
// CHECK: msr trcseqevr2, x16 // encoding: [0x90,0x02,0x11,0xd5]
|
||||||
|
// CHECK: msr trcseqrstevr, x16 // encoding: [0x90,0x06,0x11,0xd5]
|
||||||
|
// CHECK: msr trcseqstr, x25 // encoding: [0x99,0x07,0x11,0xd5]
|
||||||
|
// CHECK: msr trcextinselr, x29 // encoding: [0x9d,0x08,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntrldvr0, x20 // encoding: [0xb4,0x00,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntrldvr1, x20 // encoding: [0xb4,0x01,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntrldvr2, x22 // encoding: [0xb6,0x02,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntrldvr3, x12 // encoding: [0xac,0x03,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntctlr0, x20 // encoding: [0xb4,0x04,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntctlr1, x4 // encoding: [0xa4,0x05,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntctlr2, x8 // encoding: [0xa8,0x06,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntctlr3, x16 // encoding: [0xb0,0x07,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntvr0, x5 // encoding: [0xa5,0x08,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntvr1, x27 // encoding: [0xbb,0x09,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntvr2, x21 // encoding: [0xb5,0x0a,0x11,0xd5]
|
||||||
|
// CHECK: msr trccntvr3, x8 // encoding: [0xa8,0x0b,0x11,0xd5]
|
||||||
|
// CHECK: msr trcimspec0, x6 // encoding: [0xe6,0x00,0x11,0xd5]
|
||||||
|
// CHECK: msr trcimspec1, x27 // encoding: [0xfb,0x01,0x11,0xd5]
|
||||||
|
// CHECK: msr trcimspec2, x23 // encoding: [0xf7,0x02,0x11,0xd5]
|
||||||
|
// CHECK: msr trcimspec3, x15 // encoding: [0xef,0x03,0x11,0xd5]
|
||||||
|
// CHECK: msr trcimspec4, x13 // encoding: [0xed,0x04,0x11,0xd5]
|
||||||
|
// CHECK: msr trcimspec5, x25 // encoding: [0xf9,0x05,0x11,0xd5]
|
||||||
|
// CHECK: msr trcimspec6, x19 // encoding: [0xf3,0x06,0x11,0xd5]
|
||||||
|
// CHECK: msr trcimspec7, x27 // encoding: [0xfb,0x07,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr2, x4 // encoding: [0x04,0x12,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr3, x0 // encoding: [0x00,0x13,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr4, x21 // encoding: [0x15,0x14,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr5, x8 // encoding: [0x08,0x15,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr6, x20 // encoding: [0x14,0x16,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr7, x11 // encoding: [0x0b,0x17,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr8, x18 // encoding: [0x12,0x18,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr9, x24 // encoding: [0x18,0x19,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr10, x15 // encoding: [0x0f,0x1a,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr11, x21 // encoding: [0x15,0x1b,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr12, x4 // encoding: [0x04,0x1c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr13, x28 // encoding: [0x1c,0x1d,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr14, x3 // encoding: [0x03,0x1e,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr15, x20 // encoding: [0x14,0x1f,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr16, x12 // encoding: [0x2c,0x10,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr17, x17 // encoding: [0x31,0x11,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr18, x10 // encoding: [0x2a,0x12,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr19, x11 // encoding: [0x2b,0x13,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr20, x3 // encoding: [0x23,0x14,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr21, x18 // encoding: [0x32,0x15,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr22, x26 // encoding: [0x3a,0x16,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr23, x5 // encoding: [0x25,0x17,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr24, x25 // encoding: [0x39,0x18,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr25, x5 // encoding: [0x25,0x19,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr26, x4 // encoding: [0x24,0x1a,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr27, x20 // encoding: [0x34,0x1b,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr28, x5 // encoding: [0x25,0x1c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr29, x10 // encoding: [0x2a,0x1d,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr30, x24 // encoding: [0x38,0x1e,0x11,0xd5]
|
||||||
|
// CHECK: msr trcrsctlr31, x20 // encoding: [0x34,0x1f,0x11,0xd5]
|
||||||
|
// CHECK: msr trcssccr0, x23 // encoding: [0x57,0x10,0x11,0xd5]
|
||||||
|
// CHECK: msr trcssccr1, x27 // encoding: [0x5b,0x11,0x11,0xd5]
|
||||||
|
// CHECK: msr trcssccr2, x27 // encoding: [0x5b,0x12,0x11,0xd5]
|
||||||
|
// CHECK: msr trcssccr3, x6 // encoding: [0x46,0x13,0x11,0xd5]
|
||||||
|
// CHECK: msr trcssccr4, x3 // encoding: [0x43,0x14,0x11,0xd5]
|
||||||
|
// CHECK: msr trcssccr5, x12 // encoding: [0x4c,0x15,0x11,0xd5]
|
||||||
|
// CHECK: msr trcssccr6, x7 // encoding: [0x47,0x16,0x11,0xd5]
|
||||||
|
// CHECK: msr trcssccr7, x6 // encoding: [0x46,0x17,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsscsr0, x20 // encoding: [0x54,0x18,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsscsr1, x17 // encoding: [0x51,0x19,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsscsr2, x11 // encoding: [0x4b,0x1a,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsscsr3, x4 // encoding: [0x44,0x1b,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsscsr4, x14 // encoding: [0x4e,0x1c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsscsr5, x22 // encoding: [0x56,0x1d,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsscsr6, x3 // encoding: [0x43,0x1e,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsscsr7, x11 // encoding: [0x4b,0x1f,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsspcicr0, x2 // encoding: [0x62,0x10,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsspcicr1, x3 // encoding: [0x63,0x11,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsspcicr2, x5 // encoding: [0x65,0x12,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsspcicr3, x7 // encoding: [0x67,0x13,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsspcicr4, x11 // encoding: [0x6b,0x14,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsspcicr5, x13 // encoding: [0x6d,0x15,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsspcicr6, x17 // encoding: [0x71,0x16,0x11,0xd5]
|
||||||
|
// CHECK: msr trcsspcicr7, x23 // encoding: [0x77,0x17,0x11,0xd5]
|
||||||
|
// CHECK: msr trcpdcr, x3 // encoding: [0x83,0x14,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr0, x6 // encoding: [0x06,0x20,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr1, x20 // encoding: [0x14,0x22,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr2, x25 // encoding: [0x19,0x24,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr3, x1 // encoding: [0x01,0x26,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr4, x28 // encoding: [0x1c,0x28,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr5, x15 // encoding: [0x0f,0x2a,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr6, x25 // encoding: [0x19,0x2c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr7, x12 // encoding: [0x0c,0x2e,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr8, x5 // encoding: [0x25,0x20,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr9, x25 // encoding: [0x39,0x22,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr10, x13 // encoding: [0x2d,0x24,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr11, x10 // encoding: [0x2a,0x26,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr12, x19 // encoding: [0x33,0x28,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr13, x10 // encoding: [0x2a,0x2a,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr14, x19 // encoding: [0x33,0x2c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacvr15, x2 // encoding: [0x22,0x2e,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr0, x15 // encoding: [0x4f,0x20,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr1, x13 // encoding: [0x4d,0x22,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr2, x8 // encoding: [0x48,0x24,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr3, x1 // encoding: [0x41,0x26,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr4, x11 // encoding: [0x4b,0x28,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr5, x8 // encoding: [0x48,0x2a,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr6, x24 // encoding: [0x58,0x2c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr7, x6 // encoding: [0x46,0x2e,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr8, x23 // encoding: [0x77,0x20,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr9, x5 // encoding: [0x65,0x22,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr10, x11 // encoding: [0x6b,0x24,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr11, x11 // encoding: [0x6b,0x26,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr12, x3 // encoding: [0x63,0x28,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr13, x28 // encoding: [0x7c,0x2a,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr14, x25 // encoding: [0x79,0x2c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcacatr15, x4 // encoding: [0x64,0x2e,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcvr0, x6 // encoding: [0x86,0x20,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcvr1, x3 // encoding: [0x83,0x24,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcvr2, x5 // encoding: [0x85,0x28,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcvr3, x11 // encoding: [0x8b,0x2c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcvr4, x9 // encoding: [0xa9,0x20,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcvr5, x14 // encoding: [0xae,0x24,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcvr6, x10 // encoding: [0xaa,0x28,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcvr7, x12 // encoding: [0xac,0x2c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcmr0, x8 // encoding: [0xc8,0x20,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcmr1, x8 // encoding: [0xc8,0x24,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcmr2, x22 // encoding: [0xd6,0x28,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcmr3, x22 // encoding: [0xd6,0x2c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcmr4, x5 // encoding: [0xe5,0x20,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcmr5, x16 // encoding: [0xf0,0x24,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcmr6, x27 // encoding: [0xfb,0x28,0x11,0xd5]
|
||||||
|
// CHECK: msr trcdvcmr7, x21 // encoding: [0xf5,0x2c,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcvr0, x8 // encoding: [0x08,0x30,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcvr1, x6 // encoding: [0x06,0x32,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcvr2, x9 // encoding: [0x09,0x34,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcvr3, x8 // encoding: [0x08,0x36,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcvr4, x3 // encoding: [0x03,0x38,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcvr5, x21 // encoding: [0x15,0x3a,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcvr6, x12 // encoding: [0x0c,0x3c,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcvr7, x7 // encoding: [0x07,0x3e,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcvr0, x4 // encoding: [0x24,0x30,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcvr1, x3 // encoding: [0x23,0x32,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcvr2, x9 // encoding: [0x29,0x34,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcvr3, x17 // encoding: [0x31,0x36,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcvr4, x14 // encoding: [0x2e,0x38,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcvr5, x12 // encoding: [0x2c,0x3a,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcvr6, x10 // encoding: [0x2a,0x3c,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcvr7, x3 // encoding: [0x23,0x3e,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcctlr0, x14 // encoding: [0x4e,0x30,0x11,0xd5]
|
||||||
|
// CHECK: msr trccidcctlr1, x22 // encoding: [0x56,0x31,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcctlr0, x8 // encoding: [0x48,0x32,0x11,0xd5]
|
||||||
|
// CHECK: msr trcvmidcctlr1, x15 // encoding: [0x4f,0x33,0x11,0xd5]
|
||||||
|
// CHECK: msr trcitctrl, x1 // encoding: [0x81,0x70,0x11,0xd5]
|
||||||
|
// CHECK: msr trcclaimset, x7 // encoding: [0xc7,0x78,0x11,0xd5]
|
||||||
|
// CHECK: msr trcclaimclr, x29 // encoding: [0xdd,0x79,0x11,0xd5]
|
||||||
736
test/MC/Disassembler/AArch64/trace-regs.txt
Normal file
736
test/MC/Disassembler/AArch64/trace-regs.txt
Normal file
@ -0,0 +1,736 @@
|
|||||||
|
# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s
|
||||||
|
|
||||||
|
0x8 0x3 0x31 0xd5
|
||||||
|
# CHECK: mrs x8, trcstatr
|
||||||
|
0xc9 0x0 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trcidr8
|
||||||
|
0xcb 0x1 0x31 0xd5
|
||||||
|
# CHECK: mrs x11, trcidr9
|
||||||
|
0xd9 0x2 0x31 0xd5
|
||||||
|
# CHECK: mrs x25, trcidr10
|
||||||
|
0xc7 0x3 0x31 0xd5
|
||||||
|
# CHECK: mrs x7, trcidr11
|
||||||
|
0xc7 0x4 0x31 0xd5
|
||||||
|
# CHECK: mrs x7, trcidr12
|
||||||
|
0xc6 0x5 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trcidr13
|
||||||
|
0xfb 0x8 0x31 0xd5
|
||||||
|
# CHECK: mrs x27, trcidr0
|
||||||
|
0xfd 0x9 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcidr1
|
||||||
|
0xe4 0xa 0x31 0xd5
|
||||||
|
# CHECK: mrs x4, trcidr2
|
||||||
|
0xe8 0xb 0x31 0xd5
|
||||||
|
# CHECK: mrs x8, trcidr3
|
||||||
|
0xef 0xc 0x31 0xd5
|
||||||
|
# CHECK: mrs x15, trcidr4
|
||||||
|
0xf4 0xd 0x31 0xd5
|
||||||
|
# CHECK: mrs x20, trcidr5
|
||||||
|
0xe6 0xe 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trcidr6
|
||||||
|
0xe6 0xf 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trcidr7
|
||||||
|
0x98 0x11 0x31 0xd5
|
||||||
|
# CHECK: mrs x24, trcoslsr
|
||||||
|
0x92 0x15 0x31 0xd5
|
||||||
|
# CHECK: mrs x18, trcpdsr
|
||||||
|
0xdc 0x7a 0x31 0xd5
|
||||||
|
# CHECK: mrs x28, trcdevaff0
|
||||||
|
0xc5 0x7b 0x31 0xd5
|
||||||
|
# CHECK: mrs x5, trcdevaff1
|
||||||
|
0xc5 0x7d 0x31 0xd5
|
||||||
|
# CHECK: mrs x5, trclsr
|
||||||
|
0xcb 0x7e 0x31 0xd5
|
||||||
|
# CHECK: mrs x11, trcauthstatus
|
||||||
|
0xcd 0x7f 0x31 0xd5
|
||||||
|
# CHECK: mrs x13, trcdevarch
|
||||||
|
0xf2 0x72 0x31 0xd5
|
||||||
|
# CHECK: mrs x18, trcdevid
|
||||||
|
0xf6 0x73 0x31 0xd5
|
||||||
|
# CHECK: mrs x22, trcdevtype
|
||||||
|
0xee 0x74 0x31 0xd5
|
||||||
|
# CHECK: mrs x14, trcpidr4
|
||||||
|
0xe5 0x75 0x31 0xd5
|
||||||
|
# CHECK: mrs x5, trcpidr5
|
||||||
|
0xe5 0x76 0x31 0xd5
|
||||||
|
# CHECK: mrs x5, trcpidr6
|
||||||
|
0xe9 0x77 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trcpidr7
|
||||||
|
0xef 0x78 0x31 0xd5
|
||||||
|
# CHECK: mrs x15, trcpidr0
|
||||||
|
0xe6 0x79 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trcpidr1
|
||||||
|
0xeb 0x7a 0x31 0xd5
|
||||||
|
# CHECK: mrs x11, trcpidr2
|
||||||
|
0xf4 0x7b 0x31 0xd5
|
||||||
|
# CHECK: mrs x20, trcpidr3
|
||||||
|
0xf1 0x7c 0x31 0xd5
|
||||||
|
# CHECK: mrs x17, trccidr0
|
||||||
|
0xe2 0x7d 0x31 0xd5
|
||||||
|
# CHECK: mrs x2, trccidr1
|
||||||
|
0xf4 0x7e 0x31 0xd5
|
||||||
|
# CHECK: mrs x20, trccidr2
|
||||||
|
0xe4 0x7f 0x31 0xd5
|
||||||
|
# CHECK: mrs x4, trccidr3
|
||||||
|
0xb 0x1 0x31 0xd5
|
||||||
|
# CHECK: mrs x11, trcprgctlr
|
||||||
|
0x17 0x2 0x31 0xd5
|
||||||
|
# CHECK: mrs x23, trcprocselr
|
||||||
|
0xd 0x4 0x31 0xd5
|
||||||
|
# CHECK: mrs x13, trcconfigr
|
||||||
|
0x17 0x6 0x31 0xd5
|
||||||
|
# CHECK: mrs x23, trcauxctlr
|
||||||
|
0x9 0x8 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trceventctl0r
|
||||||
|
0x10 0x9 0x31 0xd5
|
||||||
|
# CHECK: mrs x16, trceventctl1r
|
||||||
|
0x4 0xb 0x31 0xd5
|
||||||
|
# CHECK: mrs x4, trcstallctlr
|
||||||
|
0xe 0xc 0x31 0xd5
|
||||||
|
# CHECK: mrs x14, trctsctlr
|
||||||
|
0x18 0xd 0x31 0xd5
|
||||||
|
# CHECK: mrs x24, trcsyncpr
|
||||||
|
0x1c 0xe 0x31 0xd5
|
||||||
|
# CHECK: mrs x28, trcccctlr
|
||||||
|
0xf 0xf 0x31 0xd5
|
||||||
|
# CHECK: mrs x15, trcbbctlr
|
||||||
|
0x21 0x0 0x31 0xd5
|
||||||
|
# CHECK: mrs x1, trctraceidr
|
||||||
|
0x34 0x1 0x31 0xd5
|
||||||
|
# CHECK: mrs x20, trcqctlr
|
||||||
|
0x42 0x0 0x31 0xd5
|
||||||
|
# CHECK: mrs x2, trcvictlr
|
||||||
|
0x4c 0x1 0x31 0xd5
|
||||||
|
# CHECK: mrs x12, trcviiectlr
|
||||||
|
0x50 0x2 0x31 0xd5
|
||||||
|
# CHECK: mrs x16, trcvissctlr
|
||||||
|
0x48 0x3 0x31 0xd5
|
||||||
|
# CHECK: mrs x8, trcvipcssctlr
|
||||||
|
0x5b 0x8 0x31 0xd5
|
||||||
|
# CHECK: mrs x27, trcvdctlr
|
||||||
|
0x49 0x9 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trcvdsacctlr
|
||||||
|
0x40 0xa 0x31 0xd5
|
||||||
|
# CHECK: mrs x0, trcvdarcctlr
|
||||||
|
0x8d 0x0 0x31 0xd5
|
||||||
|
# CHECK: mrs x13, trcseqevr0
|
||||||
|
0x8b 0x1 0x31 0xd5
|
||||||
|
# CHECK: mrs x11, trcseqevr1
|
||||||
|
0x9a 0x2 0x31 0xd5
|
||||||
|
# CHECK: mrs x26, trcseqevr2
|
||||||
|
0x8e 0x6 0x31 0xd5
|
||||||
|
# CHECK: mrs x14, trcseqrstevr
|
||||||
|
0x84 0x7 0x31 0xd5
|
||||||
|
# CHECK: mrs x4, trcseqstr
|
||||||
|
0x91 0x8 0x31 0xd5
|
||||||
|
# CHECK: mrs x17, trcextinselr
|
||||||
|
0xb5 0x0 0x31 0xd5
|
||||||
|
# CHECK: mrs x21, trccntrldvr0
|
||||||
|
0xaa 0x1 0x31 0xd5
|
||||||
|
# CHECK: mrs x10, trccntrldvr1
|
||||||
|
0xb4 0x2 0x31 0xd5
|
||||||
|
# CHECK: mrs x20, trccntrldvr2
|
||||||
|
0xa5 0x3 0x31 0xd5
|
||||||
|
# CHECK: mrs x5, trccntrldvr3
|
||||||
|
0xb1 0x4 0x31 0xd5
|
||||||
|
# CHECK: mrs x17, trccntctlr0
|
||||||
|
0xa1 0x5 0x31 0xd5
|
||||||
|
# CHECK: mrs x1, trccntctlr1
|
||||||
|
0xb1 0x6 0x31 0xd5
|
||||||
|
# CHECK: mrs x17, trccntctlr2
|
||||||
|
0xa6 0x7 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trccntctlr3
|
||||||
|
0xbc 0x8 0x31 0xd5
|
||||||
|
# CHECK: mrs x28, trccntvr0
|
||||||
|
0xb7 0x9 0x31 0xd5
|
||||||
|
# CHECK: mrs x23, trccntvr1
|
||||||
|
0xa9 0xa 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trccntvr2
|
||||||
|
0xa6 0xb 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trccntvr3
|
||||||
|
0xf8 0x0 0x31 0xd5
|
||||||
|
# CHECK: mrs x24, trcimspec0
|
||||||
|
0xf8 0x1 0x31 0xd5
|
||||||
|
# CHECK: mrs x24, trcimspec1
|
||||||
|
0xef 0x2 0x31 0xd5
|
||||||
|
# CHECK: mrs x15, trcimspec2
|
||||||
|
0xea 0x3 0x31 0xd5
|
||||||
|
# CHECK: mrs x10, trcimspec3
|
||||||
|
0xfd 0x4 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcimspec4
|
||||||
|
0xf2 0x5 0x31 0xd5
|
||||||
|
# CHECK: mrs x18, trcimspec5
|
||||||
|
0xfd 0x6 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcimspec6
|
||||||
|
0xe2 0x7 0x31 0xd5
|
||||||
|
# CHECK: mrs x2, trcimspec7
|
||||||
|
0x8 0x12 0x31 0xd5
|
||||||
|
# CHECK: mrs x8, trcrsctlr2
|
||||||
|
0x0 0x13 0x31 0xd5
|
||||||
|
# CHECK: mrs x0, trcrsctlr3
|
||||||
|
0xc 0x14 0x31 0xd5
|
||||||
|
# CHECK: mrs x12, trcrsctlr4
|
||||||
|
0x1a 0x15 0x31 0xd5
|
||||||
|
# CHECK: mrs x26, trcrsctlr5
|
||||||
|
0x1d 0x16 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcrsctlr6
|
||||||
|
0x11 0x17 0x31 0xd5
|
||||||
|
# CHECK: mrs x17, trcrsctlr7
|
||||||
|
0x0 0x18 0x31 0xd5
|
||||||
|
# CHECK: mrs x0, trcrsctlr8
|
||||||
|
0x1 0x19 0x31 0xd5
|
||||||
|
# CHECK: mrs x1, trcrsctlr9
|
||||||
|
0x11 0x1a 0x31 0xd5
|
||||||
|
# CHECK: mrs x17, trcrsctlr10
|
||||||
|
0x15 0x1b 0x31 0xd5
|
||||||
|
# CHECK: mrs x21, trcrsctlr11
|
||||||
|
0x1 0x1c 0x31 0xd5
|
||||||
|
# CHECK: mrs x1, trcrsctlr12
|
||||||
|
0x8 0x1d 0x31 0xd5
|
||||||
|
# CHECK: mrs x8, trcrsctlr13
|
||||||
|
0x18 0x1e 0x31 0xd5
|
||||||
|
# CHECK: mrs x24, trcrsctlr14
|
||||||
|
0x0 0x1f 0x31 0xd5
|
||||||
|
# CHECK: mrs x0, trcrsctlr15
|
||||||
|
0x22 0x10 0x31 0xd5
|
||||||
|
# CHECK: mrs x2, trcrsctlr16
|
||||||
|
0x3d 0x11 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcrsctlr17
|
||||||
|
0x36 0x12 0x31 0xd5
|
||||||
|
# CHECK: mrs x22, trcrsctlr18
|
||||||
|
0x26 0x13 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trcrsctlr19
|
||||||
|
0x3a 0x14 0x31 0xd5
|
||||||
|
# CHECK: mrs x26, trcrsctlr20
|
||||||
|
0x3a 0x15 0x31 0xd5
|
||||||
|
# CHECK: mrs x26, trcrsctlr21
|
||||||
|
0x24 0x16 0x31 0xd5
|
||||||
|
# CHECK: mrs x4, trcrsctlr22
|
||||||
|
0x2c 0x17 0x31 0xd5
|
||||||
|
# CHECK: mrs x12, trcrsctlr23
|
||||||
|
0x21 0x18 0x31 0xd5
|
||||||
|
# CHECK: mrs x1, trcrsctlr24
|
||||||
|
0x20 0x19 0x31 0xd5
|
||||||
|
# CHECK: mrs x0, trcrsctlr25
|
||||||
|
0x31 0x1a 0x31 0xd5
|
||||||
|
# CHECK: mrs x17, trcrsctlr26
|
||||||
|
0x28 0x1b 0x31 0xd5
|
||||||
|
# CHECK: mrs x8, trcrsctlr27
|
||||||
|
0x2a 0x1c 0x31 0xd5
|
||||||
|
# CHECK: mrs x10, trcrsctlr28
|
||||||
|
0x39 0x1d 0x31 0xd5
|
||||||
|
# CHECK: mrs x25, trcrsctlr29
|
||||||
|
0x2c 0x1e 0x31 0xd5
|
||||||
|
# CHECK: mrs x12, trcrsctlr30
|
||||||
|
0x2b 0x1f 0x31 0xd5
|
||||||
|
# CHECK: mrs x11, trcrsctlr31
|
||||||
|
0x52 0x10 0x31 0xd5
|
||||||
|
# CHECK: mrs x18, trcssccr0
|
||||||
|
0x4c 0x11 0x31 0xd5
|
||||||
|
# CHECK: mrs x12, trcssccr1
|
||||||
|
0x43 0x12 0x31 0xd5
|
||||||
|
# CHECK: mrs x3, trcssccr2
|
||||||
|
0x42 0x13 0x31 0xd5
|
||||||
|
# CHECK: mrs x2, trcssccr3
|
||||||
|
0x55 0x14 0x31 0xd5
|
||||||
|
# CHECK: mrs x21, trcssccr4
|
||||||
|
0x4a 0x15 0x31 0xd5
|
||||||
|
# CHECK: mrs x10, trcssccr5
|
||||||
|
0x56 0x16 0x31 0xd5
|
||||||
|
# CHECK: mrs x22, trcssccr6
|
||||||
|
0x57 0x17 0x31 0xd5
|
||||||
|
# CHECK: mrs x23, trcssccr7
|
||||||
|
0x57 0x18 0x31 0xd5
|
||||||
|
# CHECK: mrs x23, trcsscsr0
|
||||||
|
0x53 0x19 0x31 0xd5
|
||||||
|
# CHECK: mrs x19, trcsscsr1
|
||||||
|
0x59 0x1a 0x31 0xd5
|
||||||
|
# CHECK: mrs x25, trcsscsr2
|
||||||
|
0x51 0x1b 0x31 0xd5
|
||||||
|
# CHECK: mrs x17, trcsscsr3
|
||||||
|
0x53 0x1c 0x31 0xd5
|
||||||
|
# CHECK: mrs x19, trcsscsr4
|
||||||
|
0x4b 0x1d 0x31 0xd5
|
||||||
|
# CHECK: mrs x11, trcsscsr5
|
||||||
|
0x45 0x1e 0x31 0xd5
|
||||||
|
# CHECK: mrs x5, trcsscsr6
|
||||||
|
0x49 0x1f 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trcsscsr7
|
||||||
|
0x9a 0x14 0x31 0xd5
|
||||||
|
# CHECK: mrs x26, trcpdcr
|
||||||
|
0x8 0x20 0x31 0xd5
|
||||||
|
# CHECK: mrs x8, trcacvr0
|
||||||
|
0xf 0x22 0x31 0xd5
|
||||||
|
# CHECK: mrs x15, trcacvr1
|
||||||
|
0x13 0x24 0x31 0xd5
|
||||||
|
# CHECK: mrs x19, trcacvr2
|
||||||
|
0x8 0x26 0x31 0xd5
|
||||||
|
# CHECK: mrs x8, trcacvr3
|
||||||
|
0x1c 0x28 0x31 0xd5
|
||||||
|
# CHECK: mrs x28, trcacvr4
|
||||||
|
0x3 0x2a 0x31 0xd5
|
||||||
|
# CHECK: mrs x3, trcacvr5
|
||||||
|
0x19 0x2c 0x31 0xd5
|
||||||
|
# CHECK: mrs x25, trcacvr6
|
||||||
|
0x18 0x2e 0x31 0xd5
|
||||||
|
# CHECK: mrs x24, trcacvr7
|
||||||
|
0x26 0x20 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trcacvr8
|
||||||
|
0x23 0x22 0x31 0xd5
|
||||||
|
# CHECK: mrs x3, trcacvr9
|
||||||
|
0x38 0x24 0x31 0xd5
|
||||||
|
# CHECK: mrs x24, trcacvr10
|
||||||
|
0x23 0x26 0x31 0xd5
|
||||||
|
# CHECK: mrs x3, trcacvr11
|
||||||
|
0x2c 0x28 0x31 0xd5
|
||||||
|
# CHECK: mrs x12, trcacvr12
|
||||||
|
0x29 0x2a 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trcacvr13
|
||||||
|
0x2e 0x2c 0x31 0xd5
|
||||||
|
# CHECK: mrs x14, trcacvr14
|
||||||
|
0x23 0x2e 0x31 0xd5
|
||||||
|
# CHECK: mrs x3, trcacvr15
|
||||||
|
0x55 0x20 0x31 0xd5
|
||||||
|
# CHECK: mrs x21, trcacatr0
|
||||||
|
0x5a 0x22 0x31 0xd5
|
||||||
|
# CHECK: mrs x26, trcacatr1
|
||||||
|
0x48 0x24 0x31 0xd5
|
||||||
|
# CHECK: mrs x8, trcacatr2
|
||||||
|
0x56 0x26 0x31 0xd5
|
||||||
|
# CHECK: mrs x22, trcacatr3
|
||||||
|
0x46 0x28 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trcacatr4
|
||||||
|
0x5d 0x2a 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcacatr5
|
||||||
|
0x45 0x2c 0x31 0xd5
|
||||||
|
# CHECK: mrs x5, trcacatr6
|
||||||
|
0x52 0x2e 0x31 0xd5
|
||||||
|
# CHECK: mrs x18, trcacatr7
|
||||||
|
0x62 0x20 0x31 0xd5
|
||||||
|
# CHECK: mrs x2, trcacatr8
|
||||||
|
0x73 0x22 0x31 0xd5
|
||||||
|
# CHECK: mrs x19, trcacatr9
|
||||||
|
0x6d 0x24 0x31 0xd5
|
||||||
|
# CHECK: mrs x13, trcacatr10
|
||||||
|
0x79 0x26 0x31 0xd5
|
||||||
|
# CHECK: mrs x25, trcacatr11
|
||||||
|
0x72 0x28 0x31 0xd5
|
||||||
|
# CHECK: mrs x18, trcacatr12
|
||||||
|
0x7d 0x2a 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcacatr13
|
||||||
|
0x69 0x2c 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trcacatr14
|
||||||
|
0x72 0x2e 0x31 0xd5
|
||||||
|
# CHECK: mrs x18, trcacatr15
|
||||||
|
0x9d 0x20 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcdvcvr0
|
||||||
|
0x8f 0x24 0x31 0xd5
|
||||||
|
# CHECK: mrs x15, trcdvcvr1
|
||||||
|
0x8f 0x28 0x31 0xd5
|
||||||
|
# CHECK: mrs x15, trcdvcvr2
|
||||||
|
0x8f 0x2c 0x31 0xd5
|
||||||
|
# CHECK: mrs x15, trcdvcvr3
|
||||||
|
0xb3 0x20 0x31 0xd5
|
||||||
|
# CHECK: mrs x19, trcdvcvr4
|
||||||
|
0xb6 0x24 0x31 0xd5
|
||||||
|
# CHECK: mrs x22, trcdvcvr5
|
||||||
|
0xbb 0x28 0x31 0xd5
|
||||||
|
# CHECK: mrs x27, trcdvcvr6
|
||||||
|
0xa1 0x2c 0x31 0xd5
|
||||||
|
# CHECK: mrs x1, trcdvcvr7
|
||||||
|
0xdd 0x20 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcdvcmr0
|
||||||
|
0xc9 0x24 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trcdvcmr1
|
||||||
|
0xc1 0x28 0x31 0xd5
|
||||||
|
# CHECK: mrs x1, trcdvcmr2
|
||||||
|
0xc2 0x2c 0x31 0xd5
|
||||||
|
# CHECK: mrs x2, trcdvcmr3
|
||||||
|
0xe5 0x20 0x31 0xd5
|
||||||
|
# CHECK: mrs x5, trcdvcmr4
|
||||||
|
0xf5 0x24 0x31 0xd5
|
||||||
|
# CHECK: mrs x21, trcdvcmr5
|
||||||
|
0xe5 0x28 0x31 0xd5
|
||||||
|
# CHECK: mrs x5, trcdvcmr6
|
||||||
|
0xe1 0x2c 0x31 0xd5
|
||||||
|
# CHECK: mrs x1, trcdvcmr7
|
||||||
|
0x15 0x30 0x31 0xd5
|
||||||
|
# CHECK: mrs x21, trccidcvr0
|
||||||
|
0x18 0x32 0x31 0xd5
|
||||||
|
# CHECK: mrs x24, trccidcvr1
|
||||||
|
0x18 0x34 0x31 0xd5
|
||||||
|
# CHECK: mrs x24, trccidcvr2
|
||||||
|
0xc 0x36 0x31 0xd5
|
||||||
|
# CHECK: mrs x12, trccidcvr3
|
||||||
|
0xa 0x38 0x31 0xd5
|
||||||
|
# CHECK: mrs x10, trccidcvr4
|
||||||
|
0x9 0x3a 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trccidcvr5
|
||||||
|
0x6 0x3c 0x31 0xd5
|
||||||
|
# CHECK: mrs x6, trccidcvr6
|
||||||
|
0x14 0x3e 0x31 0xd5
|
||||||
|
# CHECK: mrs x20, trccidcvr7
|
||||||
|
0x34 0x30 0x31 0xd5
|
||||||
|
# CHECK: mrs x20, trcvmidcvr0
|
||||||
|
0x34 0x32 0x31 0xd5
|
||||||
|
# CHECK: mrs x20, trcvmidcvr1
|
||||||
|
0x3a 0x34 0x31 0xd5
|
||||||
|
# CHECK: mrs x26, trcvmidcvr2
|
||||||
|
0x21 0x36 0x31 0xd5
|
||||||
|
# CHECK: mrs x1, trcvmidcvr3
|
||||||
|
0x2e 0x38 0x31 0xd5
|
||||||
|
# CHECK: mrs x14, trcvmidcvr4
|
||||||
|
0x3b 0x3a 0x31 0xd5
|
||||||
|
# CHECK: mrs x27, trcvmidcvr5
|
||||||
|
0x3d 0x3c 0x31 0xd5
|
||||||
|
# CHECK: mrs x29, trcvmidcvr6
|
||||||
|
0x31 0x3e 0x31 0xd5
|
||||||
|
# CHECK: mrs x17, trcvmidcvr7
|
||||||
|
0x4a 0x30 0x31 0xd5
|
||||||
|
# CHECK: mrs x10, trccidcctlr0
|
||||||
|
0x44 0x31 0x31 0xd5
|
||||||
|
# CHECK: mrs x4, trccidcctlr1
|
||||||
|
0x49 0x32 0x31 0xd5
|
||||||
|
# CHECK: mrs x9, trcvmidcctlr0
|
||||||
|
0x4b 0x33 0x31 0xd5
|
||||||
|
# CHECK: mrs x11, trcvmidcctlr1
|
||||||
|
0x96 0x70 0x31 0xd5
|
||||||
|
# CHECK: mrs x22, trcitctrl
|
||||||
|
0xd7 0x78 0x31 0xd5
|
||||||
|
# CHECK: mrs x23, trcclaimset
|
||||||
|
0xce 0x79 0x31 0xd5
|
||||||
|
# CHECK: mrs x14, trcclaimclr
|
||||||
|
0x9c 0x10 0x11 0xd5
|
||||||
|
# CHECK: msr trcoslar, x28
|
||||||
|
0xce 0x7c 0x11 0xd5
|
||||||
|
# CHECK: msr trclar, x14
|
||||||
|
0xa 0x1 0x11 0xd5
|
||||||
|
# CHECK: msr trcprgctlr, x10
|
||||||
|
0x1b 0x2 0x11 0xd5
|
||||||
|
# CHECK: msr trcprocselr, x27
|
||||||
|
0x18 0x4 0x11 0xd5
|
||||||
|
# CHECK: msr trcconfigr, x24
|
||||||
|
0x8 0x6 0x11 0xd5
|
||||||
|
# CHECK: msr trcauxctlr, x8
|
||||||
|
0x10 0x8 0x11 0xd5
|
||||||
|
# CHECK: msr trceventctl0r, x16
|
||||||
|
0x1b 0x9 0x11 0xd5
|
||||||
|
# CHECK: msr trceventctl1r, x27
|
||||||
|
0x1a 0xb 0x11 0xd5
|
||||||
|
# CHECK: msr trcstallctlr, x26
|
||||||
|
0x0 0xc 0x11 0xd5
|
||||||
|
# CHECK: msr trctsctlr, x0
|
||||||
|
0xe 0xd 0x11 0xd5
|
||||||
|
# CHECK: msr trcsyncpr, x14
|
||||||
|
0x8 0xe 0x11 0xd5
|
||||||
|
# CHECK: msr trcccctlr, x8
|
||||||
|
0x6 0xf 0x11 0xd5
|
||||||
|
# CHECK: msr trcbbctlr, x6
|
||||||
|
0x37 0x0 0x11 0xd5
|
||||||
|
# CHECK: msr trctraceidr, x23
|
||||||
|
0x25 0x1 0x11 0xd5
|
||||||
|
# CHECK: msr trcqctlr, x5
|
||||||
|
0x40 0x0 0x11 0xd5
|
||||||
|
# CHECK: msr trcvictlr, x0
|
||||||
|
0x40 0x1 0x11 0xd5
|
||||||
|
# CHECK: msr trcviiectlr, x0
|
||||||
|
0x41 0x2 0x11 0xd5
|
||||||
|
# CHECK: msr trcvissctlr, x1
|
||||||
|
0x40 0x3 0x11 0xd5
|
||||||
|
# CHECK: msr trcvipcssctlr, x0
|
||||||
|
0x47 0x8 0x11 0xd5
|
||||||
|
# CHECK: msr trcvdctlr, x7
|
||||||
|
0x52 0x9 0x11 0xd5
|
||||||
|
# CHECK: msr trcvdsacctlr, x18
|
||||||
|
0x58 0xa 0x11 0xd5
|
||||||
|
# CHECK: msr trcvdarcctlr, x24
|
||||||
|
0x9c 0x0 0x11 0xd5
|
||||||
|
# CHECK: msr trcseqevr0, x28
|
||||||
|
0x95 0x1 0x11 0xd5
|
||||||
|
# CHECK: msr trcseqevr1, x21
|
||||||
|
0x90 0x2 0x11 0xd5
|
||||||
|
# CHECK: msr trcseqevr2, x16
|
||||||
|
0x90 0x6 0x11 0xd5
|
||||||
|
# CHECK: msr trcseqrstevr, x16
|
||||||
|
0x99 0x7 0x11 0xd5
|
||||||
|
# CHECK: msr trcseqstr, x25
|
||||||
|
0x9d 0x8 0x11 0xd5
|
||||||
|
# CHECK: msr trcextinselr, x29
|
||||||
|
0xb4 0x0 0x11 0xd5
|
||||||
|
# CHECK: msr trccntrldvr0, x20
|
||||||
|
0xb4 0x1 0x11 0xd5
|
||||||
|
# CHECK: msr trccntrldvr1, x20
|
||||||
|
0xb6 0x2 0x11 0xd5
|
||||||
|
# CHECK: msr trccntrldvr2, x22
|
||||||
|
0xac 0x3 0x11 0xd5
|
||||||
|
# CHECK: msr trccntrldvr3, x12
|
||||||
|
0xb4 0x4 0x11 0xd5
|
||||||
|
# CHECK: msr trccntctlr0, x20
|
||||||
|
0xa4 0x5 0x11 0xd5
|
||||||
|
# CHECK: msr trccntctlr1, x4
|
||||||
|
0xa8 0x6 0x11 0xd5
|
||||||
|
# CHECK: msr trccntctlr2, x8
|
||||||
|
0xb0 0x7 0x11 0xd5
|
||||||
|
# CHECK: msr trccntctlr3, x16
|
||||||
|
0xa5 0x8 0x11 0xd5
|
||||||
|
# CHECK: msr trccntvr0, x5
|
||||||
|
0xbb 0x9 0x11 0xd5
|
||||||
|
# CHECK: msr trccntvr1, x27
|
||||||
|
0xb5 0xa 0x11 0xd5
|
||||||
|
# CHECK: msr trccntvr2, x21
|
||||||
|
0xa8 0xb 0x11 0xd5
|
||||||
|
# CHECK: msr trccntvr3, x8
|
||||||
|
0xe6 0x0 0x11 0xd5
|
||||||
|
# CHECK: msr trcimspec0, x6
|
||||||
|
0xfb 0x1 0x11 0xd5
|
||||||
|
# CHECK: msr trcimspec1, x27
|
||||||
|
0xf7 0x2 0x11 0xd5
|
||||||
|
# CHECK: msr trcimspec2, x23
|
||||||
|
0xef 0x3 0x11 0xd5
|
||||||
|
# CHECK: msr trcimspec3, x15
|
||||||
|
0xed 0x4 0x11 0xd5
|
||||||
|
# CHECK: msr trcimspec4, x13
|
||||||
|
0xf9 0x5 0x11 0xd5
|
||||||
|
# CHECK: msr trcimspec5, x25
|
||||||
|
0xf3 0x6 0x11 0xd5
|
||||||
|
# CHECK: msr trcimspec6, x19
|
||||||
|
0xfb 0x7 0x11 0xd5
|
||||||
|
# CHECK: msr trcimspec7, x27
|
||||||
|
0x4 0x12 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr2, x4
|
||||||
|
0x0 0x13 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr3, x0
|
||||||
|
0x15 0x14 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr4, x21
|
||||||
|
0x8 0x15 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr5, x8
|
||||||
|
0x14 0x16 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr6, x20
|
||||||
|
0xb 0x17 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr7, x11
|
||||||
|
0x12 0x18 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr8, x18
|
||||||
|
0x18 0x19 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr9, x24
|
||||||
|
0xf 0x1a 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr10, x15
|
||||||
|
0x15 0x1b 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr11, x21
|
||||||
|
0x4 0x1c 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr12, x4
|
||||||
|
0x1c 0x1d 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr13, x28
|
||||||
|
0x3 0x1e 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr14, x3
|
||||||
|
0x14 0x1f 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr15, x20
|
||||||
|
0x2c 0x10 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr16, x12
|
||||||
|
0x31 0x11 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr17, x17
|
||||||
|
0x2a 0x12 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr18, x10
|
||||||
|
0x2b 0x13 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr19, x11
|
||||||
|
0x23 0x14 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr20, x3
|
||||||
|
0x32 0x15 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr21, x18
|
||||||
|
0x3a 0x16 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr22, x26
|
||||||
|
0x25 0x17 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr23, x5
|
||||||
|
0x39 0x18 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr24, x25
|
||||||
|
0x25 0x19 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr25, x5
|
||||||
|
0x24 0x1a 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr26, x4
|
||||||
|
0x34 0x1b 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr27, x20
|
||||||
|
0x25 0x1c 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr28, x5
|
||||||
|
0x2a 0x1d 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr29, x10
|
||||||
|
0x38 0x1e 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr30, x24
|
||||||
|
0x34 0x1f 0x11 0xd5
|
||||||
|
# CHECK: msr trcrsctlr31, x20
|
||||||
|
0x57 0x10 0x11 0xd5
|
||||||
|
# CHECK: msr trcssccr0, x23
|
||||||
|
0x5b 0x11 0x11 0xd5
|
||||||
|
# CHECK: msr trcssccr1, x27
|
||||||
|
0x5b 0x12 0x11 0xd5
|
||||||
|
# CHECK: msr trcssccr2, x27
|
||||||
|
0x46 0x13 0x11 0xd5
|
||||||
|
# CHECK: msr trcssccr3, x6
|
||||||
|
0x43 0x14 0x11 0xd5
|
||||||
|
# CHECK: msr trcssccr4, x3
|
||||||
|
0x4c 0x15 0x11 0xd5
|
||||||
|
# CHECK: msr trcssccr5, x12
|
||||||
|
0x47 0x16 0x11 0xd5
|
||||||
|
# CHECK: msr trcssccr6, x7
|
||||||
|
0x46 0x17 0x11 0xd5
|
||||||
|
# CHECK: msr trcssccr7, x6
|
||||||
|
0x54 0x18 0x11 0xd5
|
||||||
|
# CHECK: msr trcsscsr0, x20
|
||||||
|
0x51 0x19 0x11 0xd5
|
||||||
|
# CHECK: msr trcsscsr1, x17
|
||||||
|
0x4b 0x1a 0x11 0xd5
|
||||||
|
# CHECK: msr trcsscsr2, x11
|
||||||
|
0x44 0x1b 0x11 0xd5
|
||||||
|
# CHECK: msr trcsscsr3, x4
|
||||||
|
0x4e 0x1c 0x11 0xd5
|
||||||
|
# CHECK: msr trcsscsr4, x14
|
||||||
|
0x56 0x1d 0x11 0xd5
|
||||||
|
# CHECK: msr trcsscsr5, x22
|
||||||
|
0x43 0x1e 0x11 0xd5
|
||||||
|
# CHECK: msr trcsscsr6, x3
|
||||||
|
0x4b 0x1f 0x11 0xd5
|
||||||
|
# CHECK: msr trcsscsr7, x11
|
||||||
|
0x83 0x14 0x11 0xd5
|
||||||
|
# CHECK: msr trcpdcr, x3
|
||||||
|
0x6 0x20 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr0, x6
|
||||||
|
0x14 0x22 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr1, x20
|
||||||
|
0x19 0x24 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr2, x25
|
||||||
|
0x1 0x26 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr3, x1
|
||||||
|
0x1c 0x28 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr4, x28
|
||||||
|
0xf 0x2a 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr5, x15
|
||||||
|
0x19 0x2c 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr6, x25
|
||||||
|
0xc 0x2e 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr7, x12
|
||||||
|
0x25 0x20 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr8, x5
|
||||||
|
0x39 0x22 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr9, x25
|
||||||
|
0x2d 0x24 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr10, x13
|
||||||
|
0x2a 0x26 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr11, x10
|
||||||
|
0x33 0x28 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr12, x19
|
||||||
|
0x2a 0x2a 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr13, x10
|
||||||
|
0x33 0x2c 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr14, x19
|
||||||
|
0x22 0x2e 0x11 0xd5
|
||||||
|
# CHECK: msr trcacvr15, x2
|
||||||
|
0x4f 0x20 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr0, x15
|
||||||
|
0x4d 0x22 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr1, x13
|
||||||
|
0x48 0x24 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr2, x8
|
||||||
|
0x41 0x26 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr3, x1
|
||||||
|
0x4b 0x28 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr4, x11
|
||||||
|
0x48 0x2a 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr5, x8
|
||||||
|
0x58 0x2c 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr6, x24
|
||||||
|
0x46 0x2e 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr7, x6
|
||||||
|
0x77 0x20 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr8, x23
|
||||||
|
0x65 0x22 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr9, x5
|
||||||
|
0x6b 0x24 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr10, x11
|
||||||
|
0x6b 0x26 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr11, x11
|
||||||
|
0x63 0x28 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr12, x3
|
||||||
|
0x7c 0x2a 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr13, x28
|
||||||
|
0x79 0x2c 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr14, x25
|
||||||
|
0x64 0x2e 0x11 0xd5
|
||||||
|
# CHECK: msr trcacatr15, x4
|
||||||
|
0x86 0x20 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcvr0, x6
|
||||||
|
0x83 0x24 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcvr1, x3
|
||||||
|
0x85 0x28 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcvr2, x5
|
||||||
|
0x8b 0x2c 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcvr3, x11
|
||||||
|
0xa9 0x20 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcvr4, x9
|
||||||
|
0xae 0x24 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcvr5, x14
|
||||||
|
0xaa 0x28 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcvr6, x10
|
||||||
|
0xac 0x2c 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcvr7, x12
|
||||||
|
0xc8 0x20 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcmr0, x8
|
||||||
|
0xc8 0x24 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcmr1, x8
|
||||||
|
0xd6 0x28 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcmr2, x22
|
||||||
|
0xd6 0x2c 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcmr3, x22
|
||||||
|
0xe5 0x20 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcmr4, x5
|
||||||
|
0xf0 0x24 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcmr5, x16
|
||||||
|
0xfb 0x28 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcmr6, x27
|
||||||
|
0xf5 0x2c 0x11 0xd5
|
||||||
|
# CHECK: msr trcdvcmr7, x21
|
||||||
|
0x8 0x30 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcvr0, x8
|
||||||
|
0x6 0x32 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcvr1, x6
|
||||||
|
0x9 0x34 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcvr2, x9
|
||||||
|
0x8 0x36 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcvr3, x8
|
||||||
|
0x3 0x38 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcvr4, x3
|
||||||
|
0x15 0x3a 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcvr5, x21
|
||||||
|
0xc 0x3c 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcvr6, x12
|
||||||
|
0x7 0x3e 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcvr7, x7
|
||||||
|
0x24 0x30 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcvr0, x4
|
||||||
|
0x23 0x32 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcvr1, x3
|
||||||
|
0x29 0x34 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcvr2, x9
|
||||||
|
0x31 0x36 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcvr3, x17
|
||||||
|
0x2e 0x38 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcvr4, x14
|
||||||
|
0x2c 0x3a 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcvr5, x12
|
||||||
|
0x2a 0x3c 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcvr6, x10
|
||||||
|
0x23 0x3e 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcvr7, x3
|
||||||
|
0x4e 0x30 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcctlr0, x14
|
||||||
|
0x56 0x31 0x11 0xd5
|
||||||
|
# CHECK: msr trccidcctlr1, x22
|
||||||
|
0x48 0x32 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcctlr0, x8
|
||||||
|
0x4f 0x33 0x11 0xd5
|
||||||
|
# CHECK: msr trcvmidcctlr1, x15
|
||||||
|
0x81 0x70 0x11 0xd5
|
||||||
|
# CHECK: msr trcitctrl, x1
|
||||||
|
0xc7 0x78 0x11 0xd5
|
||||||
|
# CHECK: msr trcclaimset, x7
|
||||||
|
0xdd 0x79 0x11 0xd5
|
||||||
|
# CHECK: msr trcclaimclr, x29
|
||||||
|
|
||||||
|
|
||||||
Loading…
Reference in New Issue
Block a user