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MachineFunctionInfo for AArch64 in MIR
Starting with hasRedZone adding MachineFunctionInfo to be put in the YAML for MIR files. Split out of: D78062 Based on implementation for MachineFunctionInfo for WebAssembly Differential Revision: https://reviews.llvm.org/D78173 Patch by Andrew Litteken! (AndrewLitteken)
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32
lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
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32
lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
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@ -0,0 +1,32 @@
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//=- AArch64MachineFunctionInfo.cpp - AArch64 Machine Function Info ---------=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements AArch64-specific per-machine-function
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/// information.
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64MachineFunctionInfo.h"
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using namespace llvm;
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yaml::AArch64FunctionInfo::AArch64FunctionInfo(
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const llvm::AArch64FunctionInfo &MFI)
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: HasRedZone(MFI.hasRedZone()) {}
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void yaml::AArch64FunctionInfo::mappingImpl(yaml::IO &YamlIO) {
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MappingTraits<AArch64FunctionInfo>::mapping(YamlIO, *this);
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}
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void AArch64FunctionInfo::initializeBaseYamlFields(
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const yaml::AArch64FunctionInfo &YamlMFI) {
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if (YamlMFI.HasRedZone.hasValue())
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HasRedZone = YamlMFI.HasRedZone;
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}
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@ -18,6 +18,7 @@
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/IR/Function.h"
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@ -26,6 +27,10 @@
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namespace llvm {
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namespace yaml {
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struct AArch64FunctionInfo;
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} // end namespace yaml
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class MachineInstr;
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/// AArch64FunctionInfo - This class is derived from MachineFunctionInfo and
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@ -137,6 +142,7 @@ public:
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if (MF.getFunction().hasFnAttribute(Attribute::NoRedZone))
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HasRedZone = false;
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}
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void initializeBaseYamlFields(const yaml::AArch64FunctionInfo &YamlMFI);
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unsigned getBytesInStackArgArea() const { return BytesInStackArgArea; }
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void setBytesInStackArgArea(unsigned bytes) { BytesInStackArgArea = bytes; }
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@ -333,6 +339,25 @@ private:
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DenseMap<int, std::pair<unsigned, MCSymbol *>> JumpTableEntryInfo;
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};
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namespace yaml {
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struct AArch64FunctionInfo final : public yaml::MachineFunctionInfo {
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Optional<bool> HasRedZone;
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AArch64FunctionInfo() = default;
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AArch64FunctionInfo(const llvm::AArch64FunctionInfo &MFI);
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void mappingImpl(yaml::IO &YamlIO) override;
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~AArch64FunctionInfo() = default;
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};
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template <> struct MappingTraits<AArch64FunctionInfo> {
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static void mapping(IO &YamlIO, AArch64FunctionInfo &MFI) {
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YamlIO.mapOptional("hasRedZone", MFI.HasRedZone);
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}
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};
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} // end namespace yaml
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H
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@ -11,6 +11,7 @@
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#include "AArch64TargetMachine.h"
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#include "AArch64.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "AArch64MacroFusion.h"
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#include "AArch64Subtarget.h"
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#include "AArch64TargetObjectFile.h"
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@ -26,6 +27,7 @@
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/Localizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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#include "llvm/CodeGen/MIRParser/MIParser.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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@ -661,3 +663,24 @@ void AArch64PassConfig::addPreEmitPass() {
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// SVE bundles move prefixes with destructive operations.
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addPass(createUnpackMachineBundles(nullptr));
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}
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yaml::MachineFunctionInfo *
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AArch64TargetMachine::createDefaultFuncInfoYAML() const {
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return new yaml::AArch64FunctionInfo();
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}
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yaml::MachineFunctionInfo *
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AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
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const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
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return new yaml::AArch64FunctionInfo(*MFI);
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}
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bool AArch64TargetMachine::parseMachineFunctionInfo(
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const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
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SMDiagnostic &Error, SMRange &SourceRange) const {
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const auto &YamlMFI =
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reinterpret_cast<const yaml::AArch64FunctionInfo &>(MFI);
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MachineFunction &MF = PFS.MF;
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MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
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return false;
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}
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@ -49,6 +49,14 @@ public:
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return TLOF.get();
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}
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yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
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yaml::MachineFunctionInfo *
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convertFuncInfoToYAML(const MachineFunction &MF) const override;
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bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
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PerFunctionMIParsingState &PFS,
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SMDiagnostic &Error,
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SMRange &SourceRange) const override;
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private:
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bool isLittle;
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};
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@ -48,6 +48,7 @@ add_llvm_target(AArch64CodeGen
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AArch64InstructionSelector.cpp
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AArch64LegalizerInfo.cpp
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AArch64LoadStoreOptimizer.cpp
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AArch64MachineFunctionInfo.cpp
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AArch64MacroFusion.cpp
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AArch64MCInstLower.cpp
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AArch64PreLegalizerCombiner.cpp
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21
test/CodeGen/AArch64/function-info-noredzone-present.ll
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test/CodeGen/AArch64/function-info-noredzone-present.ll
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; RUN: llc -mtriple=aarch64--- --verify-machineinstrs -stop-before=finalize-isel -simplify-mir -o - < %s | FileCheck %s
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; Here we check thatt the noredzone attribute is carried through the machine
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; IR generation and is put in MachineFunctionInfo
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define void @baz() {
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entry:
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; CHECK-LABEL: name: baz
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; CHECK: machineFunctionInfo: {}
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ret void
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}
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define void @bar() #0 {
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entry:
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; CHECK-LABEL: name: bar
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; CHECK: machineFunctionInfo:
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; CHECK-NEXT: hasRedZone: false
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ret void
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}
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attributes #0 = { noredzone }
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59
test/CodeGen/MIR/AArch64/function-info-noredzone-present.mir
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59
test/CodeGen/MIR/AArch64/function-info-noredzone-present.mir
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# RUN: llc -mtriple=aarch64--- --verify-machineinstrs -simplify-mir -run-pass none %s -o - | FileCheck %s
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# This test checks for persistence of the hasRedZone attribute through a
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# llc transformation that shouldn't do anything
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# CHECK-NAME: name: foo
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# CHECK-LABEL: machineFunctionInfo: {}
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---
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name: foo
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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RET_ReallyLR
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...
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# CHECK-LABEL: name: bar
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# CHECK: machineFunctionInfo:
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# CHECK-NEXT: hasRedZone: false
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---
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name: bar
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo:
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hasRedZone: false
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body: |
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bb.0:
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RET_ReallyLR
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...
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# CHECK-LABEL: name: baz
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# CHECK: machineFunctionInfo:
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# CHECK-NEXT: hasRedZone: true
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---
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name: baz
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo:
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hasRedZone: true
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body: |
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bb.0.entry:
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RET_ReallyLR
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...
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