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[SelectionDAG] TargetLowering::SimplifyDemandedBits how to properly calculate KnownZero bits for ISD::SETCC and ISD::AssertZExt

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Summary:
For SETCC we aren't calculating the KnownZero bits at all. I've copied the code from computeKnownZero over for this.

For AssertZExt we were only setting KnownZero for bits that were demanded. But the upper bits are zero whether they were demanded or not.

I'm interested in fixing this because my belief is the first part of the ISD::AND handling code in SimplifyDemandedBits largely exists because of these two bugs. In that code we go to computeKnownBits for the LHS and optimize a RHS constant. Because computeKnownBits handles SETCC and AssertZExt correctly we get better information sometimes than when we call SimplifyDemandedBits on the LHS later. With these two issues fixed in SimplifyDemandedBits I was able to remove that computeKnownBits call and still pass all X86 tests. I'll submit that change in a separate patch.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31715

llvm-svn: 299839
This commit is contained in:
Craig Topper 2017-04-10 07:06:44 +00:00
parent 405f938399
commit 25a161eded
1 changed files with 5 additions and 1 deletions
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6
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -791,6 +791,10 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// TODO: Should we check for other forms of sign-bit comparisons? // TODO: Should we check for other forms of sign-bit comparisons?
// Examples: X <= -1, X >= 0 // Examples: X <= -1, X >= 0
} }
if (getBooleanContents(Op0.getValueType()) ==
TargetLowering::ZeroOrOneBooleanContent &&
BitWidth > 1)
KnownZero.setBitsFrom(1);
break; break;
} }
case ISD::SHL: case ISD::SHL:
@ -1233,7 +1237,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
return true; return true;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero |= ~InMask & NewMask; KnownZero |= ~InMask;
break; break;
} }
case ISD::BITCAST: case ISD::BITCAST: