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[PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under bit Mask in LLVM/Clang
This patch implements builtins for the following prototypes: unsigned long long __builtin_cntlzdm (unsigned long long, unsigned long long) unsigned long long __builtin_cnttzdm (unsigned long long, unsigned long long) vector unsigned long long vec_cntlzm (vector unsigned long long, vector unsigned long long) vector unsigned long long vec_cnttzm (vector unsigned long long, vector unsigned long long) Differential Revision: https://reviews.llvm.org/D80941
This commit is contained in:
Amy Kwan
parent
762f7a192e
commit
25f513ca38
@ -68,6 +68,14 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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: GCCBuiltin<"__builtin_pextd">,
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Intrinsic <[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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// Count Leading / Trailing Zeroes under bit Mask Builtins.
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def int_ppc_cntlzdm
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: GCCBuiltin<"__builtin_cntlzdm">,
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Intrinsic <[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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def int_ppc_cnttzdm
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: GCCBuiltin<"__builtin_cnttzdm">,
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Intrinsic <[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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def int_ppc_truncf128_round_to_odd
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: GCCBuiltin<"__builtin_truncf128_round_to_odd">,
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Intrinsic <[llvm_double_ty], [llvm_f128_ty], [IntrNoMem]>;
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@ -673,6 +681,14 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
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Intrinsic<[llvm_v1i128_ty],
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[llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty],
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[IntrNoMem]>;
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// P10 Vector Count Leading / Trailing Zeroes under bit Mask Builtins.
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def int_ppc_altivec_vclzdm : GCCBuiltin<"__builtin_altivec_vclzdm">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vctzdm : GCCBuiltin<"__builtin_altivec_vctzdm">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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}
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def int_ppc_altivec_vsl : PowerPC_Vec_WWW_Intrinsic<"vsl">;
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@ -532,6 +532,22 @@ let Predicates = [IsISA3_1] in {
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def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"pextd $rA, $rS, $rB", IIC_IntGeneral,
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[(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>;
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def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vclzdm $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD,
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(int_ppc_altivec_vclzdm v2i64:$vA, v2i64:$vB))]>;
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def VCTZDM : VXForm_1<1988, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vctzdm $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD,
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(int_ppc_altivec_vctzdm v2i64:$vA, v2i64:$vB))]>;
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def CNTLZDM : XForm_6<31, 59, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"cntlzdm $rA, $rS, $rB", IIC_IntGeneral,
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[(set i64:$rA,
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(int_ppc_cntlzdm i64:$rS, i64:$rB))]>;
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def CNTTZDM : XForm_6<31, 571, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"cnttzdm $rA, $rS, $rB", IIC_IntGeneral,
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[(set i64:$rA,
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(int_ppc_cnttzdm i64:$rS, i64:$rB))]>;
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def XXGENPCVBM :
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XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
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"xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
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@ -9,6 +9,10 @@ declare <2 x i64> @llvm.ppc.altivec.vpdepd(<2 x i64>, <2 x i64>)
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declare <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64>, <2 x i64>)
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declare i64 @llvm.ppc.pdepd(i64, i64)
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declare i64 @llvm.ppc.pextd(i64, i64)
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declare <2 x i64> @llvm.ppc.altivec.vclzdm(<2 x i64>, <2 x i64>)
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declare <2 x i64> @llvm.ppc.altivec.vctzdm(<2 x i64>, <2 x i64>)
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declare i64 @llvm.ppc.cntlzdm(i64, i64)
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declare i64 @llvm.ppc.cnttzdm(i64, i64)
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define <2 x i64> @test_vpdepd(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vpdepd:
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@ -49,3 +53,43 @@ entry:
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%tmp = tail call i64 @llvm.ppc.pextd(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define <2 x i64> @test_vclzdm(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vclzdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vclzdm v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <2 x i64> @llvm.ppc.altivec.vclzdm(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %tmp
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}
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define <2 x i64> @test_vctzdm(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vctzdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vctzdm v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <2 x i64> @llvm.ppc.altivec.vctzdm(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %tmp
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}
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define i64 @test_cntlzdm(i64 %a, i64 %b) {
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; CHECK-LABEL: test_cntlzdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cntlzdm r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.cntlzdm(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define i64 @test_cnttzdm(i64 %a, i64 %b) {
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; CHECK-LABEL: test_cnttzdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cnttzdm r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.cnttzdm(i64 %a, i64 %b)
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ret i64 %tmp
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}
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@ -13,6 +13,18 @@
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# CHECK: pextd 1, 2, 4
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0x7c 0x41 0x21 0x78
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# CHECK: vclzdm 1, 2, 3
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0x10 0x22 0x1f 0x84
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# CHECK: vctzdm 1, 2, 3
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0x10 0x22 0x1f 0xc4
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# CHECK: cntlzdm 1, 3, 2
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0x7c 0x61 0x10 0x76
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# CHECK: cnttzdm 1, 3, 2
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0x7c 0x61 0x14 0x76
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# CHECK xxgenpcvbm 0, 1, 2
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0xf0 0x02 0x0f 0x28
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@ -15,6 +15,18 @@
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# CHECK-BE: pextd 1, 2, 4 # encoding: [0x7c,0x41,0x21,0x78]
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# CHECK-LE: pextd 1, 2, 4 # encoding: [0x78,0x21,0x41,0x7c]
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pextd 1, 2, 4
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# CHECK-BE: vclzdm 1, 2, 3 # encoding: [0x10,0x22,0x1f,0x84]
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# CHECK-LE: vclzdm 1, 2, 3 # encoding: [0x84,0x1f,0x22,0x10]
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vclzdm 1, 2, 3
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# CHECK-BE: vctzdm 1, 2, 3 # encoding: [0x10,0x22,0x1f,0xc4]
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# CHECK-LE: vctzdm 1, 2, 3 # encoding: [0xc4,0x1f,0x22,0x10]
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vctzdm 1, 2, 3
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# CHECK-BE: cntlzdm 1, 3, 2 # encoding: [0x7c,0x61,0x10,0x76]
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# CHECK-LE: cntlzdm 1, 3, 2 # encoding: [0x76,0x10,0x61,0x7c]
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cntlzdm 1, 3, 2
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# CHECK-BE: cnttzdm 1, 3, 2 # encoding: [0x7c,0x61,0x14,0x76]
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# CHECK-LE: cnttzdm 1, 3, 2 # encoding: [0x76,0x14,0x61,0x7c]
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cnttzdm 1, 3, 2
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# CHECK-BE: xxgenpcvbm 0, 1, 2 # encoding: [0xf0,0x02,0x0f,0x28]
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# CHECK-LE: xxgenpcvbm 0, 1, 2 # encoding: [0x28,0x0f,0x02,0xf0]
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xxgenpcvbm 0, 1, 2
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