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AMDGPU/GlobalISel: Fix G_GEP with mixed SGPR/VGPR operands
The register bank for the destination of the sample argument copy was wrong. We shouldn't be constraining each source to the result register bank. Allow constraining the original register to the right size. llvm-svn: 364928
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9db0cb6291
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@ -278,12 +278,15 @@ bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
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.add(Lo1)
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.add(Lo2)
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.addImm(0);
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi)
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MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi)
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.addDef(MRI.createVirtualRegister(CarryRC), RegState::Dead)
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.add(Hi1)
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.add(Hi2)
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.addReg(CarryReg, RegState::Kill)
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.addImm(0);
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if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI))
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return false;
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}
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
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@ -292,9 +295,8 @@ bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
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.addReg(DstHi)
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.addImm(AMDGPU::sub1);
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if (!RBI.constrainGenericRegister(DstReg, RC, MRI) ||
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!RBI.constrainGenericRegister(I.getOperand(1).getReg(), RC, MRI) ||
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!RBI.constrainGenericRegister(I.getOperand(2).getReg(), RC, MRI))
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if (!RBI.constrainGenericRegister(DstReg, RC, MRI))
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return false;
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I.eraseFromParent();
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@ -160,7 +160,7 @@ body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
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; GFX6-LABEL: name: gep_p0_sgpr_vgpr
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; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $sgpr0_sgpr1
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; GFX6: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
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@ -172,7 +172,7 @@ body: |
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; GFX6: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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; GFX8-LABEL: name: gep_p0_sgpr_vgpr
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; GFX8: $vcc_hi = IMPLICIT_DEF
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; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $sgpr0_sgpr1
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; GFX8: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
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@ -184,7 +184,7 @@ body: |
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; GFX8: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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; GFX9-LABEL: name: gep_p0_sgpr_vgpr
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; GFX9: $vcc_hi = IMPLICIT_DEF
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; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $sgpr0_sgpr1
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; GFX9: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GFX9: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
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@ -195,7 +195,7 @@ body: |
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; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %8, %subreg.sub1
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; GFX9: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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; GFX10-WAVE64-LABEL: name: gep_p0_sgpr_vgpr
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; GFX10-WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $sgpr0_sgpr1
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; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GFX10-WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX10-WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GFX10-WAVE64: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
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@ -207,7 +207,7 @@ body: |
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; GFX10-WAVE64: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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; GFX10-WAVE32-LABEL: name: gep_p0_sgpr_vgpr
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; GFX10-WAVE32: $vcc_hi = IMPLICIT_DEF
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; GFX10-WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $sgpr0_sgpr1
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; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GFX10-WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GFX10-WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GFX10-WAVE32: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
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@ -217,7 +217,7 @@ body: |
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; GFX10-WAVE32: %8:vgpr_32, dead %10:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_I32_e64_1]], 0, implicit $exec
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; GFX10-WAVE32: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_]], %subreg.sub0, %8, %subreg.sub1
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; GFX10-WAVE32: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(p0) = COPY $sgpr0_sgpr1
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%0:sgpr(p0) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = COPY $vgpr0_vgpr1
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%2:vgpr(p0) = G_GEP %0, %1
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S_ENDPGM 0, implicit %2
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@ -319,34 +319,34 @@ body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GFX6-LABEL: name: gep_p3_sgpr_vgpr
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
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; GFX6: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit %2
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; GFX8-LABEL: name: gep_p3_sgpr_vgpr
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; GFX8: $vcc_hi = IMPLICIT_DEF
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
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; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: %2:vgpr_32, dead %3:sreg_32_xm0_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit %2
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; GFX9-LABEL: name: gep_p3_sgpr_vgpr
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; GFX9: $vcc_hi = IMPLICIT_DEF
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
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; GFX10-WAVE64-LABEL: name: gep_p3_sgpr_vgpr
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; GFX10-WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
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; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GFX10-WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10-WAVE64: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; GFX10-WAVE64: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
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; GFX10-WAVE32-LABEL: name: gep_p3_sgpr_vgpr
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; GFX10-WAVE32: $vcc_hi = IMPLICIT_DEF
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; GFX10-WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
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; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GFX10-WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10-WAVE32: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; GFX10-WAVE32: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
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%0:vgpr(p3) = COPY $sgpr0
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%0:sgpr(p3) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(p3) = G_GEP %0, %1
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S_ENDPGM 0, implicit %2
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@ -12,7 +12,7 @@ legalized: true
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regBankSelected: true
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# GCN: body:
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# GCN: [[PTR:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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# GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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# Immediate offset:
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# SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0, 0
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