RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors.

Browse Source 
llvm-svn: 150173
This commit is contained in:
Benjamin Kramer 2012-02-09 12:35:37 +00:00
parent 005987fe7a
commit 260bef228a
2 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
include/llvm/Target/TargetRegisterInfo.h
View File

@ -36,7 +36,7 @@ class TargetRegisterClass {
public: public:
typedef const unsigned* iterator; typedef const unsigned* iterator;
typedef const unsigned* const_iterator; typedef const unsigned* const_iterator;
typedef const EVT* vt_iterator; typedef const MVT::SimpleValueType* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator; typedef const TargetRegisterClass* const * sc_iterator;
private: private:
virtual void anchor(); virtual void anchor();
@ -46,7 +46,8 @@ private:
const sc_iterator SuperClasses; const sc_iterator SuperClasses;
const sc_iterator SuperRegClasses; const sc_iterator SuperRegClasses;
public: public:
TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts, TargetRegisterClass(const MCRegisterClass *MC,
const MVT::SimpleValueType *vts,
const unsigned *subcm, const unsigned *subcm,
const TargetRegisterClass * const *supcs, const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *superregcs) const TargetRegisterClass * const *superregcs)
@ -110,7 +111,7 @@ public:
/// ///
bool hasType(EVT vt) const { bool hasType(EVT vt) const {
for(int i = 0; VTs[i] != MVT::Other; ++i) for(int i = 0; VTs[i] != MVT::Other; ++i)
if (VTs[i] == vt) if (EVT(VTs[i]) == vt)
return true; return true;
return false; return false;
} }

2
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -521,7 +521,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the register list now. // Emit the register list now.
OS << " // " << Name OS << " // " << Name
<< " Register Class Value Types...\n" << " Register Class Value Types...\n"
<< " static const EVT " << Name << " static const MVT::SimpleValueType " << Name
<< "[] = {\n "; << "[] = {\n ";
for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
OS << getEnumName(RC.VTs[i]) << ", "; OS << getEnumName(RC.VTs[i]) << ", ";