mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 19:12:56 +02:00
Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove one weird cast from MVT->EVT just to call getSimpleVT().
llvm-svn: 188441
This commit is contained in:
parent
681f92310a
commit
2653227b8f
@ -1933,7 +1933,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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!VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
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return false;
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} else {
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switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) {
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switch (ArgVT.SimpleTy) {
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default:
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return false;
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case MVT::i1:
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@ -3947,7 +3947,7 @@ PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
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continue;
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}
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switch (Arg.getValueType().getSimpleVT().SimpleTy) {
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switch (Arg.getSimpleValueType().SimpleTy) {
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default: llvm_unreachable("Unexpected ValueType for argument!");
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case MVT::i32:
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case MVT::i64:
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@ -3970,7 +3970,7 @@ PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
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// must be passed right-justified in the stack doubleword, and
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// in the GPR, if one is available.
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SDValue StoreOff;
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if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
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if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
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SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
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StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
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} else
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@ -4278,7 +4278,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
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continue;
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}
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switch (Arg.getValueType().getSimpleVT().SimpleTy) {
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switch (Arg.getSimpleValueType().SimpleTy) {
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default: llvm_unreachable("Unexpected ValueType for argument!");
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case MVT::i32:
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case MVT::i64:
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@ -4743,7 +4743,7 @@ SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
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Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
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SDValue Tmp;
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switch (Op.getValueType().getSimpleVT().SimpleTy) {
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switch (Op.getSimpleValueType().SimpleTy) {
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default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
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case MVT::i32:
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Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
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@ -1026,7 +1026,7 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) {
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return false;
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// Handle zero-extension from i1 to i8, which is common.
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MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()).getSimpleVT();
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MVT SrcVT = TLI.getSimpleValueType(I->getOperand(0)->getType());
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if (SrcVT.SimpleTy == MVT::i1) {
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// Set the high bits to zero.
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ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
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@ -2609,7 +2609,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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// On x86-32, only the ABCD registers have 8-bit subregisters.
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if (!Subtarget->is64Bit()) {
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const TargetRegisterClass *TRC;
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switch (N0.getValueType().getSimpleVT().SimpleTy) {
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switch (N0.getSimpleValueType().SimpleTy) {
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case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
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case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
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default: llvm_unreachable("Unsupported TEST operand type!");
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@ -2644,7 +2644,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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// Put the value in an ABCD register.
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const TargetRegisterClass *TRC;
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switch (N0.getValueType().getSimpleVT().SimpleTy) {
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switch (N0.getSimpleValueType().SimpleTy) {
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case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
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case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
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case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
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@ -3827,7 +3827,7 @@ static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
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static
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SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
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SelectionDAG &DAG) {
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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MVT VT = SVOp->getSimpleValueType(0);
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SDLoc dl(SVOp);
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if (VT != MVT::v8i32 && VT != MVT::v8f32)
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@ -4081,7 +4081,7 @@ static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
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/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
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/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
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static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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MVT VT = SVOp->getSimpleValueType(0);
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unsigned HalfSize = VT.getVectorNumElements()/2;
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@ -4296,7 +4296,7 @@ static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
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uint64_t Index =
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cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
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MVT VT = N->getValueType(0).getSimpleVT();
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MVT VT = N->getSimpleValueType(0);
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unsigned ElSize = VT.getVectorElementType().getSizeInBits();
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bool Result = (Index * ElSize) % vecWidth == 0;
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@ -4314,7 +4314,7 @@ static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
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uint64_t Index =
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cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
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MVT VT = N->getValueType(0).getSimpleVT();
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MVT VT = N->getSimpleValueType(0);
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unsigned ElSize = VT.getVectorElementType().getSizeInBits();
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bool Result = (Index * ElSize) % vecWidth == 0;
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@ -4341,7 +4341,7 @@ bool X86::isVEXTRACT256Index(SDNode *N) {
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/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
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/// Handles 128-bit and 256-bit.
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static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
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MVT VT = N->getValueType(0).getSimpleVT();
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MVT VT = N->getSimpleValueType(0);
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assert((VT.is128BitVector() || VT.is256BitVector()) &&
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"Unsupported vector type for PSHUF/SHUFP");
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@ -4371,7 +4371,7 @@ static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
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/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
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/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
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static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
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MVT VT = N->getValueType(0).getSimpleVT();
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MVT VT = N->getSimpleValueType(0);
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assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
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"Unsupported vector type for PSHUFHW");
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@ -4395,7 +4395,7 @@ static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
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/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
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/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
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static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
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MVT VT = N->getValueType(0).getSimpleVT();
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MVT VT = N->getSimpleValueType(0);
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assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
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"Unsupported vector type for PSHUFHW");
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@ -4419,7 +4419,7 @@ static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
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/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
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/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
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static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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MVT VT = SVOp->getSimpleValueType(0);
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unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
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unsigned NumElts = VT.getVectorNumElements();
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@ -4448,7 +4448,7 @@ static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
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uint64_t Index =
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cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
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MVT VecVT = N->getOperand(0).getValueType().getSimpleVT();
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MVT VecVT = N->getOperand(0).getSimpleValueType();
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MVT ElVT = VecVT.getVectorElementType();
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unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
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@ -4463,7 +4463,7 @@ static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
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uint64_t Index =
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cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
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MVT VecVT = N->getValueType(0).getSimpleVT();
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MVT VecVT = N->getSimpleValueType(0);
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MVT ElVT = VecVT.getVectorElementType();
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unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
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@ -4512,7 +4512,7 @@ bool X86::isZeroNode(SDValue Elt) {
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/// their permute mask.
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static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
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SelectionDAG &DAG) {
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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MVT VT = SVOp->getSimpleValueType(0);
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unsigned NumElems = VT.getVectorNumElements();
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SmallVector<int, 8> MaskVec;
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@ -4789,7 +4789,7 @@ static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
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/// getLegalSplat - Generate a legal splat with supported x86 shuffles
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static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
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MVT VT = V.getValueType().getSimpleVT();
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MVT VT = V.getSimpleValueType();
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SDLoc dl(V);
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if (VT.is128BitVector()) {
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@ -4815,7 +4815,7 @@ static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
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/// PromoteSplat - Splat is promoted to target supported vector shuffles.
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static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
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MVT SrcVT = SV->getValueType(0).getSimpleVT();
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MVT SrcVT = SV->getSimpleValueType(0);
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SDValue V1 = SV->getOperand(0);
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SDLoc dl(SV);
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@ -4860,7 +4860,7 @@ static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
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bool IsZero,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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MVT VT = V2.getValueType().getSimpleVT();
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MVT VT = V2.getSimpleValueType();
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SDValue V1 = IsZero
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? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
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unsigned NumElems = VT.getVectorNumElements();
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@ -4978,7 +4978,7 @@ static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
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// Recurse into target specific vector shuffles to find scalars.
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if (isTargetShuffle(Opcode)) {
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MVT ShufVT = V.getValueType().getSimpleVT();
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MVT ShufVT = V.getSimpleValueType();
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unsigned NumElems = ShufVT.getVectorNumElements();
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SmallVector<int, 16> ShuffleMask;
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bool IsUnary;
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@ -5077,7 +5077,7 @@ bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
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static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
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bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
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unsigned NumElems =
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SVOp->getValueType(0).getSimpleVT().getVectorNumElements();
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SVOp->getSimpleValueType(0).getVectorNumElements();
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unsigned NumZeros = getNumOfConsecutiveZeros(
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SVOp, NumElems, false /* check zeros from right */, DAG,
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SVOp->getMaskElt(0));
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@ -5112,7 +5112,7 @@ static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
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static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
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bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
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unsigned NumElems =
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SVOp->getValueType(0).getSimpleVT().getVectorNumElements();
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SVOp->getSimpleValueType(0).getVectorNumElements();
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unsigned NumZeros = getNumOfConsecutiveZeros(
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SVOp, NumElems, true /* check zeros from left */, DAG,
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NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
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@ -5148,7 +5148,7 @@ static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
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bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
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// Although the logic below support any bitwidth size, there are no
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// shift instructions which handle more than 128-bit vectors.
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if (!SVOp->getValueType(0).getSimpleVT().is128BitVector())
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if (!SVOp->getSimpleValueType(0).is128BitVector())
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return false;
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if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
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@ -5436,7 +5436,7 @@ static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
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if (!Subtarget->hasFp256())
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return SDValue();
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MVT VT = Op.getValueType().getSimpleVT();
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MVT VT = Op.getSimpleValueType();
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SDLoc dl(Op);
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assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
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@ -5563,7 +5563,7 @@ static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
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}
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static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
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MVT VT = Op.getValueType().getSimpleVT();
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MVT VT = Op.getSimpleValueType();
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// Skip if insert_vec_elt is not supported.
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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@ -5640,7 +5640,7 @@ static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
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SDValue
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X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
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MVT VT = Op.getValueType().getSimpleVT();
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MVT VT = Op.getSimpleValueType();
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assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
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"Unexpected type in LowerBUILD_VECTORvXi1!");
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@ -5713,7 +5713,7 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
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// res = allOnes ### CMOVNE -1, %res
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// else
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// res = allZero
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MVT InVT = In.getValueType().getSimpleVT();
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MVT InVT = In.getSimpleValueType();
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SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
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EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
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X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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@ -5742,7 +5742,7 @@ SDValue
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X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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SDLoc dl(Op);
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MVT VT = Op.getValueType().getSimpleVT();
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MVT VT = Op.getSimpleValueType();
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MVT ExtVT = VT.getVectorElementType();
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unsigned NumElems = Op.getNumOperands();
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@ -6078,7 +6078,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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// to create 256-bit vectors from two other 128-bit ones.
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static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
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SDLoc dl(Op);
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MVT ResVT = Op.getValueType().getSimpleVT();
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MVT ResVT = Op.getSimpleValueType();
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assert((ResVT.is256BitVector() ||
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ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
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@ -6107,7 +6107,7 @@ LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
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SDValue V1 = SVOp->getOperand(0);
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SDValue V2 = SVOp->getOperand(1);
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SDLoc dl(SVOp);
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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MVT VT = SVOp->getSimpleValueType(0);
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MVT EltVT = VT.getVectorElementType();
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unsigned NumElems = VT.getVectorNumElements();
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@ -6548,7 +6548,7 @@ static
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SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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MVT VT = SVOp->getSimpleValueType(0);
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SDValue V1 = SVOp->getOperand(0);
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SDValue V2 = SVOp->getOperand(1);
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SDLoc dl(SVOp);
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@ -6596,7 +6596,7 @@ SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
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static
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SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
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SelectionDAG &DAG) {
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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MVT VT = SVOp->getSimpleValueType(0);
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SDLoc dl(SVOp);
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unsigned NumElems = VT.getVectorNumElements();
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MVT NewVT;
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@ -6675,7 +6675,7 @@ LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
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if (NewOp.getNode())
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return NewOp;
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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MVT VT = SVOp->getSimpleValueType(0);
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unsigned NumElems = VT.getVectorNumElements();
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unsigned NumLaneElems = NumElems / 2;
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@ -6787,7 +6787,7 @@ LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
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SDValue V1 = SVOp->getOperand(0);
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SDValue V2 = SVOp->getOperand(1);
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SDLoc dl(SVOp);
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MVT VT = SVOp->getValueType(0).getSimpleVT();
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MVT VT = SVOp->getSimpleValueType(0);
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assert(VT.is128BitVector() && "Unsupported vector size");
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@ -7132,7 +7132,7 @@ static SDValue
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NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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MVT VT = Op.getValueType().getSimpleVT();
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MVT VT = Op.getSimpleValueType();
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SDLoc dl(Op);
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SDValue V1 = Op.getOperand(0);
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SDValue V2 = Op.getOperand(1);
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@ -7167,7 +7167,7 @@ NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
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if (ISD::isBuildVectorAllZeros(V2.getNode())) {
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SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
|
||||
if (NewOp.getNode()) {
|
||||
MVT NewVT = NewOp.getValueType().getSimpleVT();
|
||||
MVT NewVT = NewOp.getSimpleValueType();
|
||||
if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
|
||||
NewVT, true, false))
|
||||
return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
|
||||
@ -7176,7 +7176,7 @@ NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
|
||||
} else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
|
||||
SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
|
||||
if (NewOp.getNode()) {
|
||||
MVT NewVT = NewOp.getValueType().getSimpleVT();
|
||||
MVT NewVT = NewOp.getSimpleValueType();
|
||||
if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
|
||||
return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
|
||||
DAG, Subtarget, dl);
|
||||
@ -7191,7 +7191,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
|
||||
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
|
||||
SDValue V1 = Op.getOperand(0);
|
||||
SDValue V2 = Op.getOperand(1);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
SDLoc dl(Op);
|
||||
unsigned NumElems = VT.getVectorNumElements();
|
||||
bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
|
||||
@ -7511,10 +7511,10 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
|
||||
}
|
||||
|
||||
static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
SDLoc dl(Op);
|
||||
|
||||
if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector())
|
||||
if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
|
||||
return SDValue();
|
||||
|
||||
if (VT.getSizeInBits() == 8) {
|
||||
@ -7580,7 +7580,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
|
||||
return SDValue();
|
||||
|
||||
SDValue Vec = Op.getOperand(0);
|
||||
MVT VecVT = Vec.getValueType().getSimpleVT();
|
||||
MVT VecVT = Vec.getSimpleValueType();
|
||||
|
||||
// If this is a 256-bit vector result, first extract the 128-bit vector and
|
||||
// then extract the element from the 128-bit vector.
|
||||
@ -7609,7 +7609,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
|
||||
return Res;
|
||||
}
|
||||
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
// TODO: handle v16i8.
|
||||
if (VT.getSizeInBits() == 16) {
|
||||
SDValue Vec = Op.getOperand(0);
|
||||
@ -7636,7 +7636,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
|
||||
|
||||
// SHUFPS the element to the lowest double word, then movss.
|
||||
int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
|
||||
MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
|
||||
MVT VVT = Op.getOperand(0).getSimpleValueType();
|
||||
SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
|
||||
DAG.getUNDEF(VVT), Mask);
|
||||
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
|
||||
@ -7655,7 +7655,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
|
||||
// Note if the lower 64 bits of the result of the UNPCKHPD is then stored
|
||||
// to a f64mem, the whole operation is folded into a single MOVHPDmr.
|
||||
int Mask[2] = { 1, -1 };
|
||||
MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
|
||||
MVT VVT = Op.getOperand(0).getSimpleValueType();
|
||||
SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
|
||||
DAG.getUNDEF(VVT), Mask);
|
||||
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
|
||||
@ -7666,7 +7666,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
|
||||
}
|
||||
|
||||
static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
MVT EltVT = VT.getVectorElementType();
|
||||
SDLoc dl(Op);
|
||||
|
||||
@ -7720,7 +7720,7 @@ static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
|
||||
|
||||
SDValue
|
||||
X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
MVT EltVT = VT.getVectorElementType();
|
||||
|
||||
SDLoc dl(Op);
|
||||
@ -7770,7 +7770,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
|
||||
LLVMContext *Context = DAG.getContext();
|
||||
SDLoc dl(Op);
|
||||
MVT OpVT = Op.getValueType().getSimpleVT();
|
||||
MVT OpVT = Op.getSimpleValueType();
|
||||
|
||||
// If this is a 256-bit vector result, first insert into a 128-bit
|
||||
// vector and then insert into the 256-bit vector.
|
||||
@ -8794,9 +8794,9 @@ X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
|
||||
|
||||
static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
|
||||
const X86Subtarget *Subtarget) {
|
||||
MVT VT = Op->getValueType(0).getSimpleVT();
|
||||
MVT VT = Op->getSimpleValueType(0);
|
||||
SDValue In = Op->getOperand(0);
|
||||
MVT InVT = In.getValueType().getSimpleVT();
|
||||
MVT InVT = In.getSimpleValueType();
|
||||
SDLoc dl(Op);
|
||||
|
||||
// Optimize vectors in AVX mode:
|
||||
@ -8847,9 +8847,9 @@ SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
|
||||
SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
SDLoc DL(Op);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
SDValue In = Op.getOperand(0);
|
||||
MVT SVT = In.getValueType().getSimpleVT();
|
||||
MVT SVT = In.getSimpleValueType();
|
||||
|
||||
if (Subtarget->hasFp256()) {
|
||||
SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
|
||||
@ -8879,9 +8879,9 @@ SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
|
||||
|
||||
SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
|
||||
SDLoc DL(Op);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
SDValue In = Op.getOperand(0);
|
||||
MVT SVT = In.getValueType().getSimpleVT();
|
||||
MVT SVT = In.getSimpleValueType();
|
||||
|
||||
if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
|
||||
// On AVX2, v4i64 -> v4i32 becomes VPERMD.
|
||||
@ -8996,7 +8996,7 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
if (VT.isVector()) {
|
||||
if (VT == MVT::v8i16)
|
||||
return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
|
||||
@ -9040,9 +9040,9 @@ SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
|
||||
|
||||
static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
|
||||
SDLoc DL(Op);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
SDValue In = Op.getOperand(0);
|
||||
MVT SVT = In.getValueType().getSimpleVT();
|
||||
MVT SVT = In.getSimpleValueType();
|
||||
|
||||
assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
|
||||
|
||||
@ -9054,7 +9054,7 @@ static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
|
||||
SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
|
||||
LLVMContext *Context = DAG.getContext();
|
||||
SDLoc dl(Op);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
MVT EltVT = VT;
|
||||
unsigned NumElts = VT == MVT::f64 ? 2 : 4;
|
||||
if (VT.isVector()) {
|
||||
@ -9088,7 +9088,7 @@ SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
|
||||
SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
|
||||
LLVMContext *Context = DAG.getContext();
|
||||
SDLoc dl(Op);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
MVT EltVT = VT;
|
||||
unsigned NumElts = VT == MVT::f64 ? 2 : 4;
|
||||
if (VT.isVector()) {
|
||||
@ -9125,8 +9125,8 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
|
||||
SDValue Op0 = Op.getOperand(0);
|
||||
SDValue Op1 = Op.getOperand(1);
|
||||
SDLoc dl(Op);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT SrcVT = Op1.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
MVT SrcVT = Op1.getSimpleValueType();
|
||||
|
||||
// If second operand is smaller, extend it first.
|
||||
if (SrcVT.bitsLT(VT)) {
|
||||
@ -9202,7 +9202,7 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
|
||||
static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
|
||||
SDValue N0 = Op.getOperand(0);
|
||||
SDLoc dl(Op);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
|
||||
// Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
|
||||
SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
|
||||
@ -9682,7 +9682,7 @@ static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
|
||||
// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
|
||||
// ones, and then concatenate the result back.
|
||||
static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
|
||||
assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
|
||||
"Unsupported value type for operation");
|
||||
@ -9714,7 +9714,7 @@ static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
|
||||
SDValue Op0 = Op.getOperand(0);
|
||||
SDValue Op1 = Op.getOperand(1);
|
||||
SDValue CC = Op.getOperand(2);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
|
||||
assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
|
||||
Op.getValueType().getScalarType() == MVT::i1 &&
|
||||
@ -9750,14 +9750,14 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SDValue Op0 = Op.getOperand(0);
|
||||
SDValue Op1 = Op.getOperand(1);
|
||||
SDValue CC = Op.getOperand(2);
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
|
||||
bool isFP = Op.getOperand(1).getValueType().getSimpleVT().isFloatingPoint();
|
||||
bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
|
||||
SDLoc dl(Op);
|
||||
|
||||
if (isFP) {
|
||||
#ifndef NDEBUG
|
||||
MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
|
||||
MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
|
||||
assert(EltVT == MVT::f32 || EltVT == MVT::f64);
|
||||
#endif
|
||||
|
||||
@ -9945,7 +9945,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
|
||||
|
||||
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
|
||||
if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
|
||||
|
||||
@ -9989,7 +9989,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
|
||||
}
|
||||
}
|
||||
|
||||
bool isFP = Op1.getValueType().getSimpleVT().isFloatingPoint();
|
||||
bool isFP = Op1.getSimpleValueType().isFloatingPoint();
|
||||
unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
|
||||
if (X86CC == X86::COND_INVALID)
|
||||
return SDValue();
|
||||
@ -10144,7 +10144,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
SDValue Cmp = Cond.getOperand(1);
|
||||
unsigned Opc = Cmp.getOpcode();
|
||||
MVT VT = Op.getValueType().getSimpleVT();
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
|
||||
bool IllegalFPCMov = false;
|
||||
if (VT.isFloatingPoint() && !VT.isVector() &&
|
||||
@ -10285,9 +10285,9 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_AVX512(SDValue Op,
|
||||
|
||||
SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
MVT VT = Op->getValueType(0).getSimpleVT();
|
||||
MVT VT = Op->getSimpleValueType(0);
|
||||
SDValue In = Op->getOperand(0);
|
||||
MVT InVT = In.getValueType().getSimpleVT();
|
||||
MVT InVT = In.getSimpleValueType();
|
||||
SDLoc dl(Op);
|
||||
|
||||
if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
|
||||
@ -12795,8 +12795,8 @@ static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
|
||||
|
||||
static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
MVT SrcVT = Op.getOperand(0).getValueType().getSimpleVT();
|
||||
MVT DstVT = Op.getValueType().getSimpleVT();
|
||||
MVT SrcVT = Op.getOperand(0).getSimpleValueType();
|
||||
MVT DstVT = Op.getSimpleValueType();
|
||||
assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
|
||||
Subtarget->hasMMX() && "Unexpected custom BITCAST");
|
||||
assert((DstVT == MVT::i64 ||
|
||||
@ -17887,7 +17887,7 @@ static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
|
||||
RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
|
||||
return false;
|
||||
|
||||
MVT VT = LHS.getValueType().getSimpleVT();
|
||||
MVT VT = LHS.getSimpleValueType();
|
||||
|
||||
assert((VT.is128BitVector() || VT.is256BitVector()) &&
|
||||
"Unsupported vector type for horizontal add/sub");
|
||||
|
Loading…
Reference in New Issue
Block a user