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R600/SI: Remove isel mubuf legalization
We legalize mubuf instructions post-instruction selection, so this code is no longer needed. llvm-svn: 230352
This commit is contained in:
Tom Stellard
parent
afcf85da25
commit
266ed1f528
@ -1752,16 +1752,6 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
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}
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/// \brief Test if RegClass is one of the VSrc classes
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static bool isVSrc(unsigned RegClass) {
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switch(RegClass) {
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default: return false;
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case AMDGPU::VS_32RegClassID:
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case AMDGPU::VS_64RegClassID:
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return true;
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}
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}
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/// \brief Analyze the possible immediate value Op
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///
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/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
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@ -1792,69 +1782,6 @@ int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
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return -1;
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}
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const TargetRegisterClass *
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SITargetLowering::getRegClassForNode(SelectionDAG &DAG,
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const SDValue &Op) const {
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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if (!Op->isMachineOpcode()) {
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switch(Op->getOpcode()) {
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case ISD::CopyFromReg: {
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MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
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unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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return MRI.getRegClass(Reg);
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}
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return TRI.getPhysRegClass(Reg);
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}
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default: return nullptr;
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}
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}
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const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
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int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
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if (OpClassID != -1) {
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return TRI.getRegClass(OpClassID);
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}
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switch(Op.getMachineOpcode()) {
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case AMDGPU::COPY_TO_REGCLASS:
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// Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
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OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
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// If the COPY_TO_REGCLASS instruction is copying to a VSrc register
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// class, then the register class for the value could be either a
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// VReg or and SReg. In order to get a more accurate
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if (isVSrc(OpClassID))
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return getRegClassForNode(DAG, Op.getOperand(0));
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return TRI.getRegClass(OpClassID);
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case AMDGPU::EXTRACT_SUBREG: {
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int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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const TargetRegisterClass *SuperClass =
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getRegClassForNode(DAG, Op.getOperand(0));
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return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
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}
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case AMDGPU::REG_SEQUENCE:
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// Operand 0 is the register class id for REG_SEQUENCE instructions.
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return TRI.getRegClass(
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cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
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default:
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return getRegClassFor(Op.getSimpleValueType());
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}
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}
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/// \brief Does "Op" fit into register class "RegClass" ?
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bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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unsigned RegClass) const {
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const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
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const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
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if (!RC) {
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return false;
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}
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return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
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}
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/// \brief Helper function for adjustWritemask
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static unsigned SubIdx2Lane(unsigned Idx) {
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switch (Idx) {
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@ -1972,7 +1899,6 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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SelectionDAG &DAG) const {
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
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Node = AdjustRegClass(Node, DAG);
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if (TII->isMIMG(Node->getMachineOpcode()))
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adjustWritemask(Node, DAG);
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@ -2126,56 +2052,6 @@ MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG,
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return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
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}
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MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
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SelectionDAG &DAG) const {
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SDLoc DL(N);
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unsigned NewOpcode = N->getMachineOpcode();
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switch (N->getMachineOpcode()) {
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default: return N;
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case AMDGPU::S_LOAD_DWORD_IMM:
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NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
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// Fall-through
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case AMDGPU::S_LOAD_DWORDX2_SGPR:
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if (NewOpcode == N->getMachineOpcode()) {
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NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
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}
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// Fall-through
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case AMDGPU::S_LOAD_DWORDX4_IMM:
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case AMDGPU::S_LOAD_DWORDX4_SGPR: {
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if (NewOpcode == N->getMachineOpcode()) {
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NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
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}
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if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
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return N;
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}
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ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
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const SDValue Zero64 = DAG.getTargetConstant(0, MVT::i64);
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SDValue Ptr(DAG.getMachineNode(AMDGPU::S_MOV_B64, DL, MVT::i64, Zero64), 0);
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MachineSDNode *RSrc = wrapAddr64Rsrc(DAG, DL, Ptr);
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(SDValue(RSrc, 0));
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Ops.push_back(N->getOperand(0));
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Ops.push_back(DAG.getTargetConstant(0, MVT::i32)); // soffset
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// The immediate offset is in dwords on SI and in bytes on VI.
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if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
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Ops.push_back(DAG.getTargetConstant(Offset->getSExtValue(), MVT::i32));
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else
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Ops.push_back(DAG.getTargetConstant(Offset->getSExtValue() << 2, MVT::i32));
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// Copy remaining operands so we keep any chain and glue nodes that follow
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// the normal operands.
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Ops.append(N->op_begin() + 2, N->op_end());
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return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
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}
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}
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}
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SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const {
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@ -42,13 +42,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
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SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
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const SDValue &Op) const;
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bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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unsigned RegClass) const;
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void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
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MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
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SDValue performUCharToFloatCombine(SDNode *N,
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DAGCombinerInfo &DCI) const;
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@ -94,12 +94,10 @@ define void @no_reorder_constant_load_global_store_constant_load(i32 addrspace(1
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ret void
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}
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; XXX: Should be able to reorder this, but the laods count as ordered
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; FUNC-LABEL: @reorder_constant_load_local_store_constant_load
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; CI: buffer_load_dword
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; CI: ds_write_b32
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; CI: buffer_load_dword
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; CI: ds_write_b32
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; CI: buffer_store_dword
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define void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr) #0 {
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%ptr0 = load i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8
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