mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
Added support for caller saving
llvm-svn: 847
This commit is contained in:
Ruchira Sasanka
parent
ddb08e826c
commit
26ab9c8e61
@ -79,7 +79,7 @@ class MachineRegInfo
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// RegClassArr.pushback( new SparcFloatCCRegClass(2) );
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if(DEBUG_RA)
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cerr << "Created machine register classes." << endl;
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cout << "Created machine register classes." << endl;
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}
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@ -54,7 +54,7 @@ public:
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// This method should find a color which is not used by neighbors
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// (i.e., a false position in IsColorUsedArr) and
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virtual void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const = 0;
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virtual bool isRegVolatile(const int Reg) const = 0;
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MachineRegClassInfo(const unsigned ID, const unsigned NVR,
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const unsigned NAR): RegClassID(ID), NumOfAvailRegs(NVR),
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@ -138,6 +138,22 @@ public:
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virtual MachineInstr *
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cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
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const int RegType) const=0;
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virtual MachineInstr *
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cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
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const int Offset, const int RegType) const=0;
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virtual MachineInstr *
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cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
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const unsigned DestReg, const int RegType) const=0;
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virtual bool isRegVolatile(const int RegClassID, const int Reg) const=0;
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//virtual bool handleSpecialMInstr(const MachineInstr * MInst,
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// LiveRangeInfo& LRI, vector<RegClass *> RCL) const = 0;
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@ -153,6 +169,16 @@ public:
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virtual const string getUnifiedRegName(int UnifiedRegNum) const = 0;
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virtual int getRegType(const LiveRange *const LR) const=0;
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inline virtual unsigned getFramePointer() const=0;
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inline virtual unsigned getStackPointer() const=0;
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inline virtual int getInvalidRegNum() const=0;
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//virtual void printReg(const LiveRange *const LR) const =0;
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MachineRegInfo() { }
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@ -7,7 +7,7 @@ InterferenceGraph::InterferenceGraph(RegClass *const RC) : RegCl(RC),
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IG = NULL;
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Size = 0;
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if( DEBUG_RA) {
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cerr << "Interference graph created!" << endl;
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cout << "Interference graph created!" << endl;
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}
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}
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@ -65,7 +65,7 @@ void InterferenceGraph::setInterference(const LiveRange *const LR1,
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char *val;
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if( DEBUG_RA > 1)
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cerr << "setting intf for: [" << row << "][" << col << "]" << endl;
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cout << "setting intf for: [" << row << "][" << col << "]" << endl;
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( row > col) ? val = &IG[row][col]: val = &IG[col][row];
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@ -118,9 +118,9 @@ void InterferenceGraph::mergeIGNodesOfLRs(const LiveRange *const LR1,
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assertIGNode( SrcNode );
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if( DEBUG_RA > 1) {
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cerr << "Merging LRs: \""; LR1->printSet();
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cerr << "\" and \""; LR2->printSet();
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cerr << "\"" << endl;
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cout << "Merging LRs: \""; LR1->printSet();
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cout << "\" and \""; LR2->printSet();
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cout << "\"" << endl;
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}
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unsigned SrcDegree = SrcNode->getNumOfNeighbors();
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@ -147,10 +147,10 @@ void InterferenceGraph::mergeIGNodesOfLRs(const LiveRange *const LR1,
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setInterference(LR1, LROfNeigh );
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}
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//cerr<< " #Neighs - Neigh: ["<< NeighNode->getIndex()<< "] ";
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//cerr << NeighNode->getNumOfNeighbors();
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//cerr << " Dest: [" << DestNode->getIndex() << "] ";
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//cerr << DestNode->getNumOfNeighbors() << endl;
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//cout<< " #Neighs - Neigh: ["<< NeighNode->getIndex()<< "] ";
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//cout << NeighNode->getNumOfNeighbors();
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//cout << " Dest: [" << DestNode->getIndex() << "] ";
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//cout << DestNode->getNumOfNeighbors() << endl;
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}
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@ -193,13 +193,13 @@ void InterferenceGraph::printIG() const
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if( ! Node )
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continue; // skip empty rows
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cerr << " [" << i << "] ";
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cout << " [" << i << "] ";
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for( unsigned int j=0; j < Size; j++) {
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if( j >= i) break;
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if( IG[i][j] ) cerr << "(" << i << "," << j << ") ";
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if( IG[i][j] ) cout << "(" << i << "," << j << ") ";
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}
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cerr << endl;
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cout << endl;
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}
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}
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@ -215,10 +215,10 @@ void InterferenceGraph::printIGNodeList() const
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if( ! Node )
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continue;
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cerr << " [" << Node->getIndex() << "] ";
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cout << " [" << Node->getIndex() << "] ";
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(Node->getParentLR())->printSet();
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//int Deg = Node->getCurDegree();
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cerr << "\t <# of Neighs: " << Node->getNumOfNeighbors() << ">" << endl;
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cout << "\t <# of Neighs: " << Node->getNumOfNeighbors() << ">" << endl;
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}
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}
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@ -46,7 +46,7 @@ void LiveRangeInfo::constructLiveRanges()
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{
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if( DEBUG_RA)
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cerr << "Consturcting Live Ranges ..." << endl;
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cout << "Consturcting Live Ranges ..." << endl;
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// first find the live ranges for all incoming args of the method since
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// those LRs start from the start of the method
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@ -75,8 +75,8 @@ void LiveRangeInfo::constructLiveRanges()
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if( DEBUG_RA > 1) {
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cerr << " adding LiveRange for argument ";
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printValue( (const Value *) *ArgIt); cerr << endl;
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cout << " adding LiveRange for argument ";
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printValue( (const Value *) *ArgIt); cout << endl;
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}
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}
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@ -124,9 +124,9 @@ void LiveRangeInfo::constructLiveRanges()
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OpI.getMachineOperand().getOperandType();
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if ( OpTyp == MachineOperand::MO_CCRegister) {
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cerr << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:";
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cout << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:";
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printValue( OpI.getMachineOperand().getVRegValue() );
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cerr << endl;
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cout << endl;
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}
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}
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@ -139,8 +139,8 @@ void LiveRangeInfo::constructLiveRanges()
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// Only instruction values are accepted for live ranges here
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if( Def->getValueType() != Value::InstructionVal ) {
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cerr << "\n**%%Error: Def is not an instruction val. Def=";
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printValue( Def ); cerr << endl;
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cout << "\n**%%Error: Def is not an instruction val. Def=";
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printValue( Def ); cout << endl;
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continue;
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}
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@ -156,8 +156,8 @@ void LiveRangeInfo::constructLiveRanges()
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LiveRangeMap[ Def ] = DefRange; // update the map
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if( DEBUG_RA > 1) {
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cerr << " creating a LR for def: ";
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printValue(Def); cerr << endl;
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cout << " creating a LR for def: ";
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printValue(Def); cout << endl;
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}
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// set the register class of the new live range
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@ -171,7 +171,7 @@ void LiveRangeInfo::constructLiveRanges()
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if(isCC && DEBUG_RA) {
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cerr << "\a**created a LR for a CC reg:";
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cout << "\a**created a LR for a CC reg:";
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printValue( OpI.getMachineOperand().getVRegValue() );
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}
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@ -185,8 +185,8 @@ void LiveRangeInfo::constructLiveRanges()
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LiveRangeMap[ Def ] = DefRange;
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if( DEBUG_RA > 1) {
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cerr << " added to an existing LR for def: ";
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printValue( Def ); cerr << endl;
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cout << " added to an existing LR for def: ";
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printValue( Def ); cout << endl;
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}
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}
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@ -206,7 +206,7 @@ void LiveRangeInfo::constructLiveRanges()
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suggestRegs4CallRets();
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if( DEBUG_RA)
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cerr << "Initial Live Ranges constructed!" << endl;
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cout << "Initial Live Ranges constructed!" << endl;
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}
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@ -257,7 +257,7 @@ void LiveRangeInfo::coalesceLRs()
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*/
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if( DEBUG_RA)
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cerr << endl << "Coalscing LRs ..." << endl;
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cout << endl << "Coalscing LRs ..." << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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@ -274,9 +274,9 @@ void LiveRangeInfo::coalesceLRs()
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const MachineInstr * MInst = *MInstIterator;
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if( DEBUG_RA > 1) {
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cerr << " *Iterating over machine instr ";
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cout << " *Iterating over machine instr ";
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MInst->dump();
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cerr << endl;
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cout << endl;
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}
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@ -298,8 +298,8 @@ void LiveRangeInfo::coalesceLRs()
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//don't warn about labels
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if (!((*UseI)->getType())->isLabelType() && DEBUG_RA) {
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cerr<<" !! Warning: No LR for use "; printValue(*UseI);
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cerr << endl;
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cout<<" !! Warning: No LR for use "; printValue(*UseI);
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cout << endl;
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}
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continue; // ignore and continue
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}
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@ -345,7 +345,7 @@ void LiveRangeInfo::coalesceLRs()
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} // for all BBs
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if( DEBUG_RA)
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cerr << endl << "Coalscing Done!" << endl;
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cout << endl << "Coalscing Done!" << endl;
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}
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@ -359,11 +359,11 @@ void LiveRangeInfo::coalesceLRs()
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void LiveRangeInfo::printLiveRanges()
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{
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LiveRangeMapType::iterator HMI = LiveRangeMap.begin(); // hash map iterator
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cerr << endl << "Printing Live Ranges from Hash Map:" << endl;
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cout << endl << "Printing Live Ranges from Hash Map:" << endl;
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for( ; HMI != LiveRangeMap.end() ; HMI ++ ) {
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if( (*HMI).first && (*HMI).second ) {
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cerr <<" "; printValue((*HMI).first); cerr << "\t: ";
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((*HMI).second)->printSet(); cerr << endl;
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cout <<" "; printValue((*HMI).first); cout << "\t: ";
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((*HMI).second)->printSet(); cout << endl;
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}
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}
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}
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@ -36,7 +36,7 @@ PhyRegAlloc::PhyRegAlloc(const Method *const M,
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void PhyRegAlloc::createIGNodeListsAndIGs()
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{
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if(DEBUG_RA ) cerr << "Creating LR lists ..." << endl;
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if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
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// hash map iterator
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LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
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@ -52,8 +52,8 @@ void PhyRegAlloc::createIGNodeListsAndIGs()
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if( !L) {
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if( DEBUG_RA) {
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cerr << "\n*?!?Warning: Null liver range found for: ";
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printValue( (*HMI).first) ; cerr << endl;
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cout << "\n*?!?Warning: Null liver range found for: ";
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printValue( (*HMI).first) ; cout << endl;
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}
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continue;
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}
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@ -75,7 +75,7 @@ void PhyRegAlloc::createIGNodeListsAndIGs()
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RegClassList[ rc ]->createInterferenceGraph();
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if( DEBUG_RA)
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cerr << "LRLists Created!" << endl;
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cout << "LRLists Created!" << endl;
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}
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@ -105,8 +105,8 @@ void PhyRegAlloc::addInterference(const Value *const Def,
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for( ; LIt != LVSet->end(); ++LIt) {
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if( DEBUG_RA > 1) {
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cerr << "< Def="; printValue(Def);
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cerr << ", Lvar="; printValue( *LIt); cerr << "> ";
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cout << "< Def="; printValue(Def);
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cout << ", Lvar="; printValue( *LIt); cout << "> ";
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}
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// get the live range corresponding to live var
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@ -126,15 +126,17 @@ void PhyRegAlloc::addInterference(const Value *const Def,
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}
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//the live range of this var interferes with this call
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if( isCallInst )
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if( isCallInst ) {
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LROfVar->addCallInterference( (const Instruction *const) Def );
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// cout << "\n ++Added Call Interf to set:";
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// LROfVar->printSet();
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}
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}
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else if(DEBUG_RA > 1) {
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// we will not have LRs for values not explicitly allocated in the
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// instruction stream (e.g., constants)
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cerr << " warning: no live range for " ;
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printValue( *LIt); cerr << endl; }
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cout << " warning: no live range for " ;
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printValue( *LIt); cout << endl; }
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}
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@ -148,7 +150,7 @@ void PhyRegAlloc::addInterference(const Value *const Def,
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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if(DEBUG_RA) cerr << "Creating interference graphs ..." << endl;
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if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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@ -170,6 +172,8 @@ void PhyRegAlloc::buildInterferenceGraphs()
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const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
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// if( isCallInst) cout << "\n%%% Found call Inst:\n";
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// iterate over MI operands to find defs
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for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
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@ -181,6 +185,17 @@ void PhyRegAlloc::buildInterferenceGraphs()
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} // for all operands
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// Also add interference for any implicit definitions in a machine
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// instr (currently, only calls have this).
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unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
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if( NumOfImpRefs > 0 ) {
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for(unsigned z=0; z < NumOfImpRefs; z++)
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if( MInst->implicitRefIsDefined(z) )
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addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
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}
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} // for all machine instructions in BB
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@ -215,7 +230,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
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addInterferencesForArgs(); // add interference for method args
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if( DEBUG_RA)
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cerr << "Interference graphs calculted!" << endl;
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cout << "Interference graphs calculted!" << endl;
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}
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@ -241,16 +256,17 @@ void PhyRegAlloc::addInterferencesForArgs()
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addInterference( *ArgIt, InSet, false ); // add interferences between
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// args and LVars at start
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if( DEBUG_RA > 1) {
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cerr << " - %% adding interference for argument ";
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printValue( (const Value *) *ArgIt); cerr << endl;
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cout << " - %% adding interference for argument ";
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printValue( (const Value *) *ArgIt); cout << endl;
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}
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}
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}
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#if 0
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// This method inserts caller saving/restoring instructons before/after
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// a call machine instruction.
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//----------------------------------------------------------------------------
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@ -260,7 +276,7 @@ void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
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assert( (TM.getInstrInfo()).isCall( MInst->getOpCode() ) );
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int StackOff = 10; // ****TODO : Change
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set<unsigned> PushedRegSet();
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hash_set<unsigned> PushedRegSet;
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// Now find the LR of the return value of the call
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// The last *implicit operand* is the return value of a call
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@ -275,7 +291,7 @@ void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
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if( MInst->implicitRefIsDefined(NumOfImpRefs-1) ) {
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const Value *RetVal = CallMI->getImplicitRef(NumOfImpRefs-1);
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const Value *RetVal = MInst->getImplicitRef(NumOfImpRefs-1);
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LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
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assert( RetValLR && "No LR for RetValue of call");
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@ -287,7 +303,7 @@ void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
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}
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LiveVarSet *LVSetAft = LVI->getLiveVarSetAfterMInst(MInst, BB);
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const LiveVarSet *LVSetAft = LVI->getLiveVarSetAfterMInst(MInst, BB);
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LiveVarSet::const_iterator LIt = LVSetAft->begin();
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@ -313,20 +329,28 @@ void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
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unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
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if( PuhsedRegSet.find(Reg) == PhusedRegSet.end() ) {
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if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
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// if we haven't already pushed that register
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MachineInstr *AdI =
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MRI.saveRegOnStackMI(Reg, MRI.getFPReg(), StackOff );
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unsigned RegType = MRI.getRegType( LR );
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((AddedInstrMap[MInst])->InstrnsBefore).push_front(AdI);
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((AddedInstrMap[MInst])->InstrnsAfter).push_back(AdI);
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// Now get two instructions - to push on stack and pop from stack
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// and add them to InstrnsBefore and InstrnsAfter of the
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// call instruction
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MachineInstr *AdIBef =
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MRI.cpReg2MemMI(Reg, MRI.getFramePointer(), StackOff, RegType );
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MachineInstr *AdIAft =
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MRI.cpMem2RegMI(MRI.getFramePointer(), StackOff, Reg, RegType );
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((AddedInstrMap[MInst])->InstrnsBefore).push_front(AdIBef);
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||||
((AddedInstrMap[MInst])->InstrnsAfter).push_back(AdIAft);
|
||||
|
||||
PushedRegSet.insert( Reg );
|
||||
StackOff += 4; // ****TODO: Correct ??????
|
||||
cerr << "Inserted caller saving instr");
|
||||
cout << "\n $$$ Inserted caller saving instr";
|
||||
|
||||
} // if not already pushed
|
||||
|
||||
@ -340,7 +364,6 @@ void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// This method is called after register allocation is complete to set the
|
||||
@ -364,13 +387,17 @@ void PhyRegAlloc::updateMachineCode()
|
||||
|
||||
MachineInstr *MInst = *MInstIterator;
|
||||
|
||||
// if this machine instr is call, insert caller saving code
|
||||
|
||||
if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
|
||||
insertCallerSavingCode(MInst, *BBI );
|
||||
|
||||
// If there are instructions to be added, *before* this machine
|
||||
// instruction, add them now.
|
||||
|
||||
// If there are instructions before to be added, add them now
|
||||
// ***TODO: Add InstrnsAfter as well
|
||||
if( AddedInstrMap[ MInst ] ) {
|
||||
|
||||
deque<MachineInstr *> &IBef =
|
||||
(AddedInstrMap[MInst])->InstrnsBefore;
|
||||
deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
|
||||
|
||||
if( ! IBef.empty() ) {
|
||||
|
||||
@ -378,9 +405,9 @@ void PhyRegAlloc::updateMachineCode()
|
||||
|
||||
for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
|
||||
|
||||
cerr << "*ADDED instr opcode: ";
|
||||
cerr << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString;
|
||||
cerr << endl;
|
||||
cout << " *$* PREPENDed instr opcode: ";
|
||||
cout << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString;
|
||||
cout << endl;
|
||||
|
||||
MInstIterator = MIVec.insert( MInstIterator, *AdIt );
|
||||
++MInstIterator;
|
||||
@ -388,9 +415,6 @@ void PhyRegAlloc::updateMachineCode()
|
||||
|
||||
}
|
||||
|
||||
// restart from the topmost instruction added
|
||||
//MInst = *MInstIterator;
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -409,7 +433,7 @@ void PhyRegAlloc::updateMachineCode()
|
||||
// delete this condition checking later (must assert if Val is null)
|
||||
if( !Val) {
|
||||
if (DEBUG_RA)
|
||||
cerr << "Warning: NULL Value found for operand" << endl;
|
||||
cout << "Warning: NULL Value found for operand" << endl;
|
||||
continue;
|
||||
}
|
||||
assert( Val && "Value is NULL");
|
||||
@ -421,12 +445,13 @@ void PhyRegAlloc::updateMachineCode()
|
||||
// nothing to worry if it's a const or a label
|
||||
|
||||
if (DEBUG_RA) {
|
||||
cerr << "*NO LR for inst opcode: ";
|
||||
cerr << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
|
||||
cout << "*NO LR for inst opcode: ";
|
||||
cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
|
||||
}
|
||||
|
||||
// if register is not allocated, mark register as invalid
|
||||
if( Op.getAllocatedRegNum() == -1)
|
||||
Op.setRegForValue( 1000 ); // mark register as invalid
|
||||
Op.setRegForValue( MRI.getInvalidRegNum());
|
||||
|
||||
#if 0
|
||||
if( ((Val->getType())->isLabelType()) ||
|
||||
@ -442,16 +467,16 @@ void PhyRegAlloc::updateMachineCode()
|
||||
|
||||
//TM.getInstrInfo().isReturn(MInst->getOpCode())
|
||||
else if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ) {
|
||||
if (DEBUG_RA) cerr << endl << "RETURN found" << endl;
|
||||
if (DEBUG_RA) cout << endl << "RETURN found" << endl;
|
||||
Op.setRegForValue( MRI.getReturnAddressReg() );
|
||||
|
||||
}
|
||||
|
||||
if (Val->getValueType() == Value::InstructionVal)
|
||||
{
|
||||
cerr << "!Warning: No LiveRange for: ";
|
||||
printValue( Val); cerr << " Type: " << Val->getValueType();
|
||||
cerr << " RegVal=" << Op.getAllocatedRegNum() << endl;
|
||||
cout << "!Warning: No LiveRange for: ";
|
||||
printValue( Val); cout << " Type: " << Val->getValueType();
|
||||
cout << " RegVal=" << Op.getAllocatedRegNum() << endl;
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -467,9 +492,42 @@ void PhyRegAlloc::updateMachineCode()
|
||||
|
||||
}
|
||||
|
||||
} // for each operand
|
||||
|
||||
|
||||
// If there are instructions to be added *after* this machine
|
||||
// instruction, add them now
|
||||
|
||||
if( AddedInstrMap[ MInst ] ) {
|
||||
|
||||
deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
|
||||
|
||||
if( ! IAft.empty() ) {
|
||||
|
||||
deque<MachineInstr *>::iterator AdIt;
|
||||
|
||||
++MInstIterator; // advance to the next instruction
|
||||
|
||||
for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
|
||||
|
||||
cout << " *#* APPENDed instr opcode: ";
|
||||
cout << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString;
|
||||
cout << endl;
|
||||
|
||||
MInstIterator = MIVec.insert( MInstIterator, *AdIt );
|
||||
++MInstIterator;
|
||||
}
|
||||
|
||||
// MInsterator already points to the next instr. Since the
|
||||
// for loop also increments it, decrement it to point to the
|
||||
// instruction added last
|
||||
--MInstIterator;
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
} // for each machine instruction
|
||||
}
|
||||
}
|
||||
|
||||
@ -483,14 +541,14 @@ void PhyRegAlloc::updateMachineCode()
|
||||
void PhyRegAlloc::printMachineCode()
|
||||
{
|
||||
|
||||
cerr << endl << ";************** Method ";
|
||||
cerr << Meth->getName() << " *****************" << endl;
|
||||
cout << endl << ";************** Method ";
|
||||
cout << Meth->getName() << " *****************" << endl;
|
||||
|
||||
Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
|
||||
|
||||
for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
|
||||
|
||||
cerr << endl ; printLabel( *BBI); cerr << ": ";
|
||||
cout << endl ; printLabel( *BBI); cout << ": ";
|
||||
|
||||
// get the iterator for machine instructions
|
||||
MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
|
||||
@ -502,8 +560,8 @@ void PhyRegAlloc::printMachineCode()
|
||||
MachineInstr *const MInst = *MInstIterator;
|
||||
|
||||
|
||||
cerr << endl << "\t";
|
||||
cerr << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
|
||||
cout << endl << "\t";
|
||||
cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
|
||||
|
||||
|
||||
//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
|
||||
@ -519,14 +577,14 @@ void PhyRegAlloc::printMachineCode()
|
||||
const Value *const Val = Op.getVRegValue () ;
|
||||
// ****this code is temporary till NULL Values are fixed
|
||||
if( ! Val ) {
|
||||
cerr << "\t<*NULL*>";
|
||||
cout << "\t<*NULL*>";
|
||||
continue;
|
||||
}
|
||||
|
||||
// if a label or a constant
|
||||
if( (Val->getValueType() == Value::BasicBlockVal) ) {
|
||||
|
||||
cerr << "\t"; printLabel( Op.getVRegValue () );
|
||||
cout << "\t"; printLabel( Op.getVRegValue () );
|
||||
}
|
||||
else {
|
||||
// else it must be a register value
|
||||
@ -534,27 +592,42 @@ void PhyRegAlloc::printMachineCode()
|
||||
|
||||
//if( RegNum != 1000)
|
||||
|
||||
cerr << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
|
||||
// else cerr << "\t<*NoReg*>";
|
||||
cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
|
||||
// else cout << "\t<*NoReg*>";
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
|
||||
cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
|
||||
cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
|
||||
}
|
||||
|
||||
else
|
||||
cerr << "\t" << Op; // use dump field
|
||||
cout << "\t" << Op; // use dump field
|
||||
}
|
||||
|
||||
|
||||
|
||||
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
|
||||
if( NumOfImpRefs > 0 ) {
|
||||
|
||||
cout << "\tImplicit:";
|
||||
|
||||
for(unsigned z=0; z < NumOfImpRefs; z++) {
|
||||
printValue( MInst->getImplicitRef(z) );
|
||||
cout << "\t";
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
cerr << endl;
|
||||
} // for all machine instructions
|
||||
|
||||
}
|
||||
|
||||
cerr << endl;
|
||||
cout << endl;
|
||||
|
||||
} // for all BBs
|
||||
|
||||
cout << endl;
|
||||
}
|
||||
|
||||
|
||||
@ -617,9 +690,9 @@ void PhyRegAlloc::colorIncomingArgs()
|
||||
void PhyRegAlloc::printLabel(const Value *const Val)
|
||||
{
|
||||
if( Val->hasName() )
|
||||
cerr << Val->getName();
|
||||
cout << Val->getName();
|
||||
else
|
||||
cerr << "Label" << Val;
|
||||
cout << "Label" << Val;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -81,6 +81,9 @@ class PhyRegAlloc
|
||||
void addInterferencesForArgs();
|
||||
void createIGNodeListsAndIGs();
|
||||
void buildInterferenceGraphs();
|
||||
void insertCallerSavingCode(const MachineInstr *MInst,
|
||||
const BasicBlock *BB );
|
||||
|
||||
|
||||
inline void constructLiveRanges()
|
||||
{ LRI.constructLiveRanges(); }
|
||||
|
||||
@ -9,7 +9,7 @@ RegClass::RegClass(const Method *const M,
|
||||
IG(this), IGNodeStack(), ReservedColorList(RCL)
|
||||
{
|
||||
if( DEBUG_RA)
|
||||
cerr << "Created Reg Class: " << RegClassID << endl;
|
||||
cout << "Created Reg Class: " << RegClassID << endl;
|
||||
|
||||
// This constructor inits IG. The actual matrix is created by a call to
|
||||
// createInterferenceGraph() above.
|
||||
@ -21,7 +21,7 @@ RegClass::RegClass(const Method *const M,
|
||||
|
||||
void RegClass::colorAllRegs()
|
||||
{
|
||||
if(DEBUG_RA) cerr << "Coloring IGs ..." << endl;
|
||||
if(DEBUG_RA) cout << "Coloring IGs ..." << endl;
|
||||
|
||||
//preColorIGNodes(); // pre-color IGNodes
|
||||
pushAllIGNodes(); // push all IG Nodes
|
||||
@ -55,9 +55,9 @@ void RegClass::pushAllIGNodes()
|
||||
bool PushedAll = pushUnconstrainedIGNodes();
|
||||
|
||||
if( DEBUG_RA) {
|
||||
cerr << " Puhsed all-unconstrained IGNodes. ";
|
||||
if( PushedAll ) cerr << " No constrained nodes left.";
|
||||
cerr << endl;
|
||||
cout << " Puhsed all-unconstrained IGNodes. ";
|
||||
if( PushedAll ) cout << " No constrained nodes left.";
|
||||
cout << endl;
|
||||
}
|
||||
|
||||
if( PushedAll ) // if NO constrained nodes left
|
||||
@ -112,8 +112,8 @@ bool RegClass::pushUnconstrainedIGNodes()
|
||||
IGNode->pushOnStack(); // set OnStack and dec deg of neighs
|
||||
|
||||
if (DEBUG_RA > 1) {
|
||||
cerr << " pushed un-constrained IGNode " << IGNode->getIndex() ;
|
||||
cerr << " on to stack" << endl;
|
||||
cout << " pushed un-constrained IGNode " << IGNode->getIndex() ;
|
||||
cout << " on to stack" << endl;
|
||||
}
|
||||
}
|
||||
else pushedall = false; // we didn't push all live ranges
|
||||
@ -170,16 +170,16 @@ void RegClass::colorIGNode(IGNode *const Node)
|
||||
}
|
||||
else {
|
||||
if( DEBUG_RA ) {
|
||||
cerr << " Node " << Node->getIndex();
|
||||
cerr << " already colored with color " << Node->getColor() << endl;
|
||||
cout << " Node " << Node->getIndex();
|
||||
cout << " already colored with color " << Node->getColor() << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if( !Node->hasColor() ) {
|
||||
if( DEBUG_RA ) {
|
||||
cerr << " Node " << Node->getIndex();
|
||||
cerr << " - could not find a color (needs spilling)" << endl;
|
||||
cout << " Node " << Node->getIndex();
|
||||
cout << " - could not find a color (needs spilling)" << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -148,7 +148,7 @@ class UltraSparcRegInfo : public MachineRegInfo
|
||||
// %o0 to %o5 (cannot be changed)
|
||||
unsigned const NumOfIntArgRegs;
|
||||
unsigned const NumOfFloatArgRegs;
|
||||
unsigned const InvalidRegNum;
|
||||
int const InvalidRegNum;
|
||||
|
||||
//void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
|
||||
|
||||
@ -221,9 +221,7 @@ class UltraSparcRegInfo : public MachineRegInfo
|
||||
|
||||
|
||||
|
||||
|
||||
MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
|
||||
const int RegType) const;
|
||||
// ***TODO: See this method is necessary
|
||||
|
||||
MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
|
||||
const int RegType) const;
|
||||
@ -329,8 +327,8 @@ class UltraSparcRegInfo : public MachineRegInfo
|
||||
return reg + 32 + 64; // 32 int, 64 float
|
||||
else if( RegClassID == IntCCRegClassID )
|
||||
return 4+ 32 + 64; // only int cc reg
|
||||
else if (reg==1000) //****** TODO: Remove
|
||||
return 1000;
|
||||
else if (reg==InvalidRegNum)
|
||||
return InvalidRegNum;
|
||||
else
|
||||
assert(0 && "Invalid register class or reg number");
|
||||
|
||||
@ -347,13 +345,39 @@ class UltraSparcRegInfo : public MachineRegInfo
|
||||
else if ( reg == 64+32+4)
|
||||
return "xcc"; // only integer cc reg
|
||||
|
||||
else if (reg==1000) //****** TODO: Remove
|
||||
else if (reg== InvalidRegNum) //****** TODO: Remove
|
||||
return "<*NoReg*>";
|
||||
else
|
||||
assert(0 && "Invalid register number");
|
||||
}
|
||||
|
||||
|
||||
MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
|
||||
const int RegType) const;
|
||||
|
||||
MachineInstr * cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
|
||||
const int Offset, const int RegType) const;
|
||||
|
||||
MachineInstr * cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
|
||||
const unsigned DestReg, const int RegType) const;
|
||||
|
||||
inline bool isRegVolatile(const int RegClassID, const int Reg) const {
|
||||
return (MachineRegClassArr[RegClassID])->isRegVolatile(Reg);
|
||||
}
|
||||
|
||||
|
||||
inline unsigned getFramePointer() const {
|
||||
return SparcIntRegOrder::i6;
|
||||
}
|
||||
|
||||
inline unsigned getStackPointer() const {
|
||||
return SparcIntRegOrder::o6;
|
||||
}
|
||||
|
||||
inline int getInvalidRegNum() const {
|
||||
return InvalidRegNum;
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -495,7 +519,7 @@ const InstrClassRUsage NoneClassRUsage = {
|
||||
/*numEntries*/ 0,
|
||||
/* V[] */ {
|
||||
/*Cycle G */
|
||||
/*Cycle E */
|
||||
/*Ccle E */
|
||||
/*Cycle C */
|
||||
/*Cycle N1*/
|
||||
/*Cycle N1*/
|
||||
|
||||
@ -58,6 +58,8 @@ class SparcIntRegOrder{
|
||||
|
||||
g0, g1, g2, g3, g4, g5, g6, g7, i6, i7, o6
|
||||
|
||||
//*** NOTE: If we decide to use globals, some of them are volatile
|
||||
//**** see sparc64ABI (change isRegVloatile method below)
|
||||
|
||||
|
||||
};
|
||||
@ -91,6 +93,10 @@ class SparcIntRegClass : public MachineRegClassInfo
|
||||
|
||||
void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
|
||||
|
||||
inline bool isRegVolatile(const int Reg) const {
|
||||
return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
@ -163,6 +169,10 @@ class SparcFloatRegClass : public MachineRegClassInfo
|
||||
|
||||
void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
|
||||
|
||||
// according to Sparc 64 ABI, all %fp regs are volatile
|
||||
inline bool isRegVolatile(const int Reg) const { return true; }
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -185,6 +195,9 @@ public:
|
||||
Node->setColor(0); // only one int cc reg is available
|
||||
}
|
||||
|
||||
// *** TODO: Check this
|
||||
inline bool isRegVolatile(const int Reg) const { return true; }
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -215,6 +228,10 @@ class SparcFloatCCRegOrder{
|
||||
return FloatCCRegNames[reg];
|
||||
}
|
||||
|
||||
// according to Sparc 64 ABI, all %fp regs are volatile
|
||||
inline bool isRegVolatile(const int Reg) const { return true; }
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -233,6 +250,10 @@ public:
|
||||
Node->setColor(c);
|
||||
}
|
||||
|
||||
// *** TODO: Check this
|
||||
inline bool isRegVolatile(const int Reg) const { return true; }
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -29,7 +29,7 @@ void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr * RetMI,
|
||||
|
||||
|
||||
// TODO (Optimize):
|
||||
//Instead of setting the color, we can suggest one. In that case,
|
||||
// Instead of setting the color, we can suggest one. In that case,
|
||||
// we have to test later whether it received the suggested color.
|
||||
// In that case, a LR has to be created at the start of method.
|
||||
// It has to be done as follows (remove the setRegVal above):
|
||||
@ -393,7 +393,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
|
||||
UniRetReg = getUnifiedRegNum( RegClassID, SparcFloatRegOrder::f0);
|
||||
|
||||
|
||||
AdMI = cpReg2RegMI(UniRetLRReg, UniRetReg, RegType );
|
||||
AdMI = cpReg2RegMI(UniRetReg, UniRetLRReg, RegType );
|
||||
CallAI->InstrnsAfter.push_back( AdMI );
|
||||
|
||||
|
||||
@ -613,7 +613,7 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
|
||||
const unsigned DestReg,
|
||||
const int RegType) const {
|
||||
|
||||
assert( (SrcReg != InvalidRegNum) && (DestReg != InvalidRegNum) &&
|
||||
assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
|
||||
"Invalid Register");
|
||||
|
||||
MachineInstr * MI = NULL;
|
||||
@ -647,6 +647,107 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Copy from a register to memory. Register number must be the unified
|
||||
// register number
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
|
||||
MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
|
||||
const unsigned DestPtrReg,
|
||||
const int Offset,
|
||||
const int RegType) const {
|
||||
|
||||
|
||||
MachineInstr * MI = NULL;
|
||||
|
||||
switch( RegType ) {
|
||||
|
||||
case IntRegType:
|
||||
MI = new MachineInstr(STX, 3);
|
||||
MI->SetMachineOperand(0, DestPtrReg, false);
|
||||
MI->SetMachineOperand(1, SrcReg, false);
|
||||
MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
|
||||
(int64_t) Offset, false);
|
||||
break;
|
||||
|
||||
case FPSingleRegType:
|
||||
MI = new MachineInstr(ST, 3);
|
||||
MI->SetMachineOperand(0, DestPtrReg, false);
|
||||
MI->SetMachineOperand(1, SrcReg, false);
|
||||
MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
|
||||
(int64_t) Offset, false);
|
||||
break;
|
||||
|
||||
case FPDoubleRegType:
|
||||
MI = new MachineInstr(STD, 3);
|
||||
MI->SetMachineOperand(0, DestPtrReg, false);
|
||||
MI->SetMachineOperand(1, SrcReg, false);
|
||||
MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
|
||||
(int64_t) Offset, false);
|
||||
break;
|
||||
|
||||
default:
|
||||
assert(0 && "Unknow RegType");
|
||||
}
|
||||
|
||||
return MI;
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Copy from memory to a reg. Register number must be the unified
|
||||
// register number
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
|
||||
MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
|
||||
const int Offset,
|
||||
const unsigned DestReg,
|
||||
const int RegType) const {
|
||||
|
||||
MachineInstr * MI = NULL;
|
||||
|
||||
switch( RegType ) {
|
||||
|
||||
case IntRegType:
|
||||
MI = new MachineInstr(LDX, 3);
|
||||
MI->SetMachineOperand(0, SrcPtrReg, false);
|
||||
MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
|
||||
(int64_t) Offset, false);
|
||||
MI->SetMachineOperand(2, DestReg, false);
|
||||
break;
|
||||
|
||||
case FPSingleRegType:
|
||||
MI = new MachineInstr(LD, 3);
|
||||
MI->SetMachineOperand(0, SrcPtrReg, false);
|
||||
MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
|
||||
(int64_t) Offset, false);
|
||||
MI->SetMachineOperand(2, DestReg, false);
|
||||
|
||||
break;
|
||||
|
||||
case FPDoubleRegType:
|
||||
MI = new MachineInstr(LDD, 3);
|
||||
MI->SetMachineOperand(0, SrcPtrReg, false);
|
||||
MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
|
||||
(int64_t) Offset, false);
|
||||
MI->SetMachineOperand(2, DestReg, false);
|
||||
break;
|
||||
|
||||
default:
|
||||
assert(0 && "Unknow RegType");
|
||||
}
|
||||
|
||||
return MI;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
@ -659,7 +760,7 @@ MachineInstr * UltraSparcRegInfo::cpValue2RegMI(Value * Val,
|
||||
const unsigned DestReg,
|
||||
const int RegType) const {
|
||||
|
||||
assert( (DestReg != InvalidRegNum) && "Invalid Register");
|
||||
assert( ((int)DestReg != InvalidRegNum) && "Invalid Register");
|
||||
|
||||
/*
|
||||
unsigned MReg;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user