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[X86] Make sure we still mark the full register as implicitly defined when we shrink 256/512 bit zeroing xors to 128-bit.

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Not sure if anything really cares, but this seems like the right thing to do.

llvm-svn: 314071
This commit is contained in:
Craig Topper 2017-09-24 05:24:51 +00:00
parent 2f7c470cc7
commit 26afdb807c
1 changed files with 10 additions and 4 deletions
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14
lib/Target/X86/X86InstrInfo.cpp
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@ -7731,7 +7731,9 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
unsigned SrcReg = MIB->getOperand(0).getReg();
unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
MIB->getOperand(0).setReg(XReg);
return Expand2AddrUndef(MIB, get(X86::VXORPSrr));
Expand2AddrUndef(MIB, get(X86::VXORPSrr));
MIB.addReg(SrcReg, RegState::ImplicitDefine);
return true;
}
case X86::AVX512_128_SET0:
case X86::AVX512_FsFLD0SS:
@ -7755,8 +7757,10 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
MIB->getOperand(0).setReg(XReg);
return Expand2AddrUndef(MIB,
get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
Expand2AddrUndef(MIB,
get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
MIB.addReg(SrcReg, RegState::ImplicitDefine);
return true;
}
return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
}
@ -7766,7 +7770,9 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
if (TRI->getEncodingValue(SrcReg) < 16) {
unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
MIB->getOperand(0).setReg(XReg);
return Expand2AddrUndef(MIB, get(X86::VXORPSrr));
Expand2AddrUndef(MIB, get(X86::VXORPSrr));
MIB.addReg(SrcReg, RegState::ImplicitDefine);
return true;
}
return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
}