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During PEI, if the immediate value of sp + offset is too large (i.e. something
that would require > 3 instructions to materialize), load the immediate from a constpool entry. llvm-svn: 33667
This commit is contained in:
Evan Cheng
parent
27f0acaaec
commit
26ee4f882b
@ -18,14 +18,16 @@
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#include "ARMMachineFunctionInfo.h"
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#include "ARMRegisterInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Type.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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@ -281,7 +283,7 @@ bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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/// emitARMRegPlusImmediate - Emit a series of instructions to materialize
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/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in ARM code.
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static
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void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
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@ -323,7 +325,70 @@ static bool isLowRegister(unsigned Reg) {
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}
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}
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/// emitThumbRegPlusImmediate - Emit a series of instructions to materialize
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/// calcNumMI - Returns the number of instructions required to materialize
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/// the specific add / sub r, c instruction.
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static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
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unsigned NumBits, unsigned Scale) {
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unsigned NumMIs = 0;
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unsigned Chunk = ((1 << NumBits) - 1) * Scale;
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if (Opc == ARM::tADDrSPi) {
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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NumMIs++;
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NumBits = 8;
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Scale = 1;
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Chunk = ((1 << NumBits) - 1) * Scale;
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}
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NumMIs += Bytes / Chunk;
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if ((Bytes % Chunk) != 0)
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NumMIs++;
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if (ExtraOpc)
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NumMIs++;
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return NumMIs;
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}
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/// emitThumbRegPlusConstPool - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code. Load the immediate from a
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/// constpool entry.
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static
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void emitThumbRegPlusConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned BaseReg,
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int NumBytes, const TargetInstrInfo &TII) {
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MachineFunction &MF = *MBB.getParent();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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bool isHigh = !isLowRegister(DestReg) || !isLowRegister(BaseReg);
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bool isSub = false;
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// Subtract doesn't have high register version. Load the negative value
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// if either base or dest register is a high register.
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if (NumBytes < 0 && !isHigh) {
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isSub = true;
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NumBytes = -NumBytes;
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}
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Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
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unsigned LdReg = DestReg;
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if (DestReg == ARM::SP) {
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assert(BaseReg == ARM::SP && "Unexpected!");
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LdReg = ARM::R3;
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BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3);
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}
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// Load the constant.
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BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), LdReg).addConstantPoolIndex(Idx);
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// Emit add / sub.
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int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
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const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
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if (DestReg == ARM::SP)
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MIB.addReg(BaseReg).addReg(LdReg);
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else
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MIB.addReg(LdReg).addReg(BaseReg);
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if (DestReg == ARM::SP)
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BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12);
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}
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/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code.
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static
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void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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@ -335,10 +400,11 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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if (isSub) Bytes = -NumBytes;
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bool isMul4 = (Bytes & 3) == 0;
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bool isTwoAddr = false;
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bool DstNeBase = false;
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unsigned NumBits = 1;
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unsigned Scale = 1;
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unsigned Opc = 0;
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unsigned ExtraOpc = 0;
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int Opc = 0;
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int ExtraOpc = 0;
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if (DestReg == BaseReg && BaseReg == ARM::SP) {
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assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
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@ -359,24 +425,39 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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Scale = 4;
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Opc = ARM::tADDrSPi;
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} else {
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if (DestReg != BaseReg) {
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if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
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// If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
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unsigned Chunk = (1 << 3) - 1;
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
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.addReg(BaseReg).addImm(ThisVal);
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} else {
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BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg);
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}
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BaseReg = DestReg;
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}
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// sp = sub sp, c
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// r1 = sub sp, c
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// r8 = sub sp, c
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if (DestReg != BaseReg)
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DstNeBase = true;
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NumBits = 8;
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Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
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isTwoAddr = true;
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}
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unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
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unsigned Threshold = (DestReg == ARM::SP) ? 4 : 3;
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if (NumMIs > Threshold) {
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// This will expand into too many instructions. Load the immediate from a
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// constpool entry.
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emitThumbRegPlusConstPool(MBB, MBBI, DestReg, BaseReg, NumBytes, TII);
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return;
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}
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if (DstNeBase) {
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if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
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// If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
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unsigned Chunk = (1 << 3) - 1;
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
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.addReg(BaseReg).addImm(ThisVal);
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} else {
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BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg);
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}
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BaseReg = DestReg;
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}
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unsigned Chunk = ((1 << NumBits) - 1) * Scale;
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while (Bytes) {
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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@ -643,7 +724,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
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return;
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}
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// Otherwise, it didn't fit. Pull in what we can to simplify the immediate.
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// Otherwise, it didn't fit. Pull in what we can to simplify the immediate.
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if (AddrMode == ARMII::AddrModeTs) {
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// Thumb tLDRspi, tSTRspi. These will change to instructions that use a
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// different base register.
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