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[AArch64] Add parsing of aarch64_vector_pcs attribute.

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This patch adds parsing support for the 'aarch64_vector_pcs'
calling convention attribute to calls and function declarations.

More information describing the vector ABI and procedure call standard
can be found here:

  https://developer.arm.com/products/software-development-tools/\
                            hpc/arm-compiler-for-hpc/vector-function-abi

Reviewers: t.p.northover, rnk, rengolin, javed.absar, thegameg, SjoerdMeijer

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D51477

llvm-svn: 342030
This commit is contained in:
Sander de Smalen 2018-09-12 08:54:06 +00:00
parent 83a4513206
commit 26f87b9829
8 changed files with 27 additions and 0 deletions
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3
include/llvm/IR/CallingConv.h
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@ -220,6 +220,9 @@ namespace CallingConv {
/// shader if tessellation is in use, or otherwise the vertex shader.
AMDGPU_ES = 96,
// Calling convention between AArch64 Advanced SIMD functions
AArch64_VectorCall = 97,
/// The highest possible calling convention ID. Must be some 2^k - 1.
MaxID = 1023
};

1
lib/AsmParser/LLLexer.cpp
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@ -592,6 +592,7 @@ lltok::Kind LLLexer::LexIdentifier() {
KEYWORD(arm_apcscc);
KEYWORD(arm_aapcscc);
KEYWORD(arm_aapcs_vfpcc);
KEYWORD(aarch64_vector_pcs);
KEYWORD(msp430_intrcc);
KEYWORD(avr_intrcc);
KEYWORD(avr_signalcc);

2
lib/AsmParser/LLParser.cpp
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@ -1874,6 +1874,7 @@ void LLParser::ParseOptionalDLLStorageClass(unsigned &Res) {
/// ::= 'arm_apcscc'
/// ::= 'arm_aapcscc'
/// ::= 'arm_aapcs_vfpcc'
/// ::= 'aarch64_vector_pcs'
/// ::= 'msp430_intrcc'
/// ::= 'avr_intrcc'
/// ::= 'avr_signalcc'
@ -1917,6 +1918,7 @@ bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
case lltok::kw_arm_apcscc: CC = CallingConv::ARM_APCS; break;
case lltok::kw_arm_aapcscc: CC = CallingConv::ARM_AAPCS; break;
case lltok::kw_arm_aapcs_vfpcc:CC = CallingConv::ARM_AAPCS_VFP; break;
case lltok::kw_aarch64_vector_pcs:CC = CallingConv::AArch64_VectorCall; break;
case lltok::kw_msp430_intrcc: CC = CallingConv::MSP430_INTR; break;
case lltok::kw_avr_intrcc: CC = CallingConv::AVR_INTR; break;
case lltok::kw_avr_signalcc: CC = CallingConv::AVR_SIGNAL; break;

1
lib/AsmParser/LLToken.h
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@ -139,6 +139,7 @@ enum Kind {
kw_arm_apcscc,
kw_arm_aapcscc,
kw_arm_aapcs_vfpcc,
kw_aarch64_vector_pcs,
kw_msp430_intrcc,
kw_avr_intrcc,
kw_avr_signalcc,

1
lib/IR/AsmWriter.cpp
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@ -363,6 +363,7 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) {
case CallingConv::ARM_APCS: Out << "arm_apcscc"; break;
case CallingConv::ARM_AAPCS: Out << "arm_aapcscc"; break;
case CallingConv::ARM_AAPCS_VFP: Out << "arm_aapcs_vfpcc"; break;
case CallingConv::AArch64_VectorCall: Out << "aarch64_vector_pcs"; break;
case CallingConv::MSP430_INTR: Out << "msp430_intrcc"; break;
case CallingConv::AVR_INTR: Out << "avr_intrcc "; break;
case CallingConv::AVR_SIGNAL: Out << "avr_signalcc "; break;

2
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -2896,6 +2896,8 @@ CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
case CallingConv::Win64:
return IsVarArg ? CC_AArch64_Win64_VarArg : CC_AArch64_AAPCS;
case CallingConv::AArch64_VectorCall:
return CC_AArch64_AAPCS;
}
}

6
lib/Target/AArch64/AArch64RegisterInfo.cpp
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@ -49,6 +49,9 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CSR_AArch64_NoRegs_SaveList;
if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
return CSR_AArch64_AllRegs_SaveList;
if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall)
// FIXME: default to AAPCS until we add full support.
return CSR_AArch64_AAPCS_SaveList;
if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
@ -98,6 +101,9 @@ AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
if (CC == CallingConv::CXX_FAST_TLS)
return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask
: CSR_AArch64_CXX_TLS_Darwin_RegMask;
if (CC == CallingConv::AArch64_VectorCall)
// FIXME: default to AAPCS until we add full support.
return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
->supportSwiftError() &&
MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))

11
test/Bitcode/vector-pcs.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llvm-as %s -o - -f | llvm-dis | FileCheck %s
; RUN: llvm-as %s -o - -f | verify-uselistorder
declare aarch64_vector_pcs void @aarch64_vector_pcs()
; CHECK: declare aarch64_vector_pcs void @aarch64_vector_pcs
define void @call_aarch64_vector_pcs() {
; CHECK: call aarch64_vector_pcs void @aarch64_vector_pcs
call aarch64_vector_pcs void @aarch64_vector_pcs()
ret void
}