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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
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Jack Carter
parent
c3319a35d0
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2737a54489
@ -117,8 +117,9 @@ def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>;
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let Predicates = [HasMips64r2, HasStdEnc],
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DecoderNamespace = "Mips64" in {
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def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>,
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SRA_FM<0x3a, 1>;
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def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>, SRLV_FM<0x16, 1>;
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SRA_FM<0x3a, 1>;
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def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>,
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SRLV_FM<0x16, 1>;
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}
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let DecoderNamespace = "Mips64" in {
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@ -173,8 +174,10 @@ def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
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let DecoderNamespace = "Mips64" in {
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/// Multiply and Divide Instructions.
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def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1c>;
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def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1d>;
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def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1c>;
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def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1d>;
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def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1e>;
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def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>,
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@ -305,20 +308,21 @@ def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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def : InstAlias<"move $dst,$src", (DADDu CPU64RegsOpnd:$dst,
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def : InstAlias<"move $dst, $src", (DADDu CPU64RegsOpnd:$dst,
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CPU64RegsOpnd:$src,ZERO_64)>,
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Requires<[HasMips64]>;
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Requires<[HasMips64]>;
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def : InstAlias<"and $rs, $rt, $imm",
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(DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm)>,
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Requires<[HasMips64]>;
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Requires<[HasMips64]>;
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def : InstAlias<"slt $rs, $rt, $imm",
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(SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm)>,
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Requires<[HasMips64]>;
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Requires<[HasMips64]>;
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def : InstAlias<"xor $rs, $rt, $imm",
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(XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm)>,
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Requires<[HasMips64]>;
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def : InstAlias<"not $rt, $rs", (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64)>,
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Requires<[HasMips64]>;
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Requires<[HasMips64]>;
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def : InstAlias<"not $rt, $rs",
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(NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64)>,
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Requires<[HasMips64]>;
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def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs)>, Requires<[HasMips64]>;
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def : InstAlias<"daddu $rs, $rt, $imm",
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(DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm)>;
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@ -326,35 +330,29 @@ def : InstAlias<"dadd $rs, $rt, $imm",
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(DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm)>;
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64" in {
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def MFC0_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel),
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"mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
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def MTC0_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt),
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"mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
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def MFC2_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel),
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"mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
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def MTC2_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt),
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"mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
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def DMFC0_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel),
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def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
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(ins CPU64RegsOpnd:$rd, uimm16:$sel),
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"dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
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def DMTC0_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt),
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def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
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(ins CPU64RegsOpnd:$rt),
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"dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
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def DMFC2_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel),
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def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
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(ins CPU64RegsOpnd:$rd, uimm16:$sel),
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"dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
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def DMTC2_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt),
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def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
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(ins CPU64RegsOpnd:$rt),
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"dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
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}
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// Two operand (implicit 0 selector) versions:
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def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"dmfc0 $rt, $rd",
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(DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"dmtc0 $rt, $rd",
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(DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"dmfc2 $rt, $rd",
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(DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"dmtc2 $rt, $rd",
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(DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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// Two operand (implicit 0 selector) versions:
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def : InstAlias<"dmfc0 $rt, $rd",
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(DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0)>;
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def : InstAlias<"dmtc0 $rt, $rd",
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(DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt)>;
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def : InstAlias<"dmfc2 $rt, $rd",
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(DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0)>;
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def : InstAlias<"dmtc2 $rt, $rd",
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(DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt)>;
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@ -506,7 +506,8 @@ class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
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RegisterClass RC>:
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InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
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!strconcat(opstr, "\t$rt, $rs, $imm16"),
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[(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>;
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[(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
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IIAlu, FrmI>;
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// Jump
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class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
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@ -774,9 +775,12 @@ def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
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def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
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def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>;
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def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
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def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, ADDI_FM<0xc>;
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def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, ADDI_FM<0xd>;
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def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, ADDI_FM<0xe>;
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def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
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ADDI_FM<0xc>;
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def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
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ADDI_FM<0xd>;
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def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
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ADDI_FM<0xe>;
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def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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@ -793,9 +797,12 @@ def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
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def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
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/// Shift Instructions
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def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, SRA_FM<0, 0>;
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def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, SRA_FM<2, 0>;
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def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, SRA_FM<3, 0>;
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def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
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SRA_FM<0, 0>;
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def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
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SRA_FM<2, 0>;
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def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
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SRA_FM<3, 0>;
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def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>;
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def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
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def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>;
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@ -863,7 +870,8 @@ def RET : RetBase<CPURegs>, MTLO_FM<8>;
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/// Multiply and Divide Instructions.
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def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>;
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def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>;
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def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>;
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def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>,
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MULT_FM<0, 0x1a>;
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def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>,
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MULT_FM<0, 0x1b>;
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@ -905,16 +913,20 @@ def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
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def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
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/// Move Control Registers From/To CPU Registers
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def MFC0_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel),
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def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
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(ins CPURegsOpnd:$rd, uimm16:$sel),
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"mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
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def MTC0_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt),
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def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
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(ins CPURegsOpnd:$rt),
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"mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
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def MFC2_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel),
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def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
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(ins CPURegsOpnd:$rd, uimm16:$sel),
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"mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
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def MTC2_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt),
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def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
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(ins CPURegsOpnd:$rt),
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"mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
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//===----------------------------------------------------------------------===//
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@ -939,10 +951,10 @@ def : InstAlias<"slt $rs, $rt, $imm",
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def : InstAlias<"xor $rs, $rt, $imm",
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(XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>,
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Requires<[NotMips64]>;
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def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
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def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
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def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
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def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
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def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0)>;
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def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt)>;
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def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0)>;
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def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt)>;
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions
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@ -1,4 +1,5 @@
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# RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding | FileCheck --check-prefix=MIPS64 %s
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# RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding \
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# RUN:| FileCheck --check-prefix=MIPS64 %s
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# MIPS64: dmtc0 $12, $16, 2 # encoding: [0x40,0xac,0x80,0x02]
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# MIPS64: dmtc0 $12, $16, 0 # encoding: [0x40,0xac,0x80,0x00]
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