From 2752e0b8695a37edec715fb5755c6e1b6e8385e0 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Tue, 18 Oct 2011 18:12:09 +0000 Subject: [PATCH] ARM vqdmulh assembly parsing for the lane index operand. llvm-svn: 142386 --- lib/Target/ARM/ARMInstrNEON.td | 8 ++++---- test/MC/ARM/neont2-mul-encoding.s | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index e022f03cf00..96d8f7bf434 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -2009,8 +2009,8 @@ class N3VDInt op21_20, bits<4> op11_8, bit op4, class N3VDIntSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp> : N3VLane32<0, 1, op21_20, op11_8, 1, 0, - (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane), - NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "", + (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), + NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [(set (Ty DPR:$Vd), (Ty (IntOp (Ty DPR:$Vn), (Ty (NEONvduplane (Ty DPR_VFP2:$Vm), @@ -2020,8 +2020,8 @@ class N3VDIntSL op21_20, bits<4> op11_8, InstrItinClass itin, class N3VDIntSL16 op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp> : N3VLane16<0, 1, op21_20, op11_8, 1, 0, - (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane), - NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "", + (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), + NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [(set (Ty DPR:$Vd), (Ty (IntOp (Ty DPR:$Vn), (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> { diff --git a/test/MC/ARM/neont2-mul-encoding.s b/test/MC/ARM/neont2-mul-encoding.s index 8ad8cde9cd8..8f8fd5928ca 100644 --- a/test/MC/ARM/neont2-mul-encoding.s +++ b/test/MC/ARM/neont2-mul-encoding.s @@ -31,13 +31,13 @@ vqdmulh.s32 d16, d16, d17 vqdmulh.s16 q8, q8, q9 vqdmulh.s32 q8, q8, q9 -@ vqdmulh.s16 d11, d2, d3[0] + vqdmulh.s16 d11, d2, d3[0] @ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x0b] @ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0b] @ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x0b] @ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0b] -@ FIXME: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x92,0xef,0x43,0xbc] +@ CHECK: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x92,0xef,0x43,0xbc] vqrdmulh.s16 d16, d16, d17