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[PowerPC] Implament Load and Reserve and Store Conditional Builtins

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This patch implaments the load and reserve and store conditional
builtins for the PowerPC target, in order to have feature parody with
xlC on AIX.

Differential revision: https://reviews.llvm.org/D105236
This commit is contained in:
Albion Fung 2021-07-05 21:34:37 -05:00 committed by Albion Fung
parent 797d9342f0
commit 2776c1ab5d
5 changed files with 104 additions and 0 deletions
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10
include/llvm/IR/IntrinsicsPowerPC.td
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@ -1523,5 +1523,15 @@ let TargetPrefix = "ppc" in {
Intrinsic<[],[],[]>;
def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
Intrinsic<[],[],[]>;
def int_ppc_stdcx : GCCBuiltin<"__builtin_ppc_stdcx">,
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i64_ty],
[IntrWriteMem]>;
def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrWriteMem]>;
def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
}

5
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -1720,3 +1720,8 @@ def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
} // IsISA3_0
def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
(STDCX g8rc:$A, ForceXForm:$dst)>;
def : Pat<(int_ppc_ldarx ForceXForm:$dst),
(LDARX ForceXForm:$dst)>;

5
lib/Target/PowerPC/PPCInstrInfo.td
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@ -5411,3 +5411,8 @@ def DWBytes3210 {
// swap the high word and low word.
def : Pat<(i64 (bitreverse i64:$A)),
(OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
def : Pat<(int_ppc_lwarx ForceXForm:$dst),
(LWARX ForceXForm:$dst)>;
def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
(STWCX gprc:$A, ForceXForm:$dst)>;

35
test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll Normal file
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@ -0,0 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
declare i64 @llvm.ppc.ldarx(i8*)
define dso_local i64 @test_ldarx(i64* readnone %a) {
; CHECK-LABEL: test_ldarx:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ldarx 3, 0, 3
; CHECK-NEXT: blr
entry:
%0 = bitcast i64* %a to i8*
%1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
ret i64 %1
}
declare i32 @llvm.ppc.stdcx(i8*, i64)
define dso_local i64 @test(i64* %a, i64 %b) {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stdcx. 4, 0, 3
; CHECK-NEXT: mfocrf 3, 128
; CHECK-NEXT: srwi 3, 3, 28
; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: blr
entry:
%0 = bitcast i64* %a to i8*
%1 = tail call i32 @llvm.ppc.stdcx(i8* %0, i64 %b)
%conv = sext i32 %1 to i64
ret i64 %conv
}

49
test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll Normal file
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@ -0,0 +1,49 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-32
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64
declare i32 @llvm.ppc.lwarx(i8*)
define dso_local signext i32 @test_lwarx(i32* readnone %a) {
; CHECK-64-LABEL: test_lwarx:
; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: lwarx 3, 0, 3
; CHECK-64-NEXT: extsw 3, 3
; CHECK-64-NEXT: blr
;
; CHECK-32-LABEL: test_lwarx:
; CHECK-32: # %bb.0: # %entry
; CHECK-32-NEXT: lwarx 3, 0, 3
; CHECK-32-NEXT: blr
entry:
%0 = bitcast i32* %a to i8*
%1 = tail call i32 @llvm.ppc.lwarx(i8* %0)
ret i32 %1
}
declare i32 @llvm.ppc.stwcx(i8*, i32)
define dso_local signext i32 @test_stwcx(i32* %a, i32 signext %b) {
; CHECK-64-LABEL: test_stwcx:
; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: stwcx. 4, 0, 3
; CHECK-64-NEXT: mfocrf 3, 128
; CHECK-64-NEXT: srwi 3, 3, 28
; CHECK-64-NEXT: extsw 3, 3
; CHECK-64-NEXT: blr
;
; CHECK-32-LABEL: test_stwcx:
; CHECK-32: # %bb.0: # %entry
; CHECK-32-NEXT: stwcx. 4, 0, 3
; CHECK-32-NEXT: mfocrf 3, 128
; CHECK-32-NEXT: srwi 3, 3, 28
; CHECK-32-NEXT: blr
entry:
%0 = bitcast i32* %a to i8*
%1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %b)
ret i32 %1
}