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[Hexagon] Remove {{ *}} from testcases

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The spaces in the instructions are now consistent.

llvm-svn: 326829
This commit is contained in:
Krzysztof Parzyszek 2018-03-06 19:07:21 +00:00
parent 45734a8fc3
commit 2790a1e6e3
30 changed files with 197 additions and 198 deletions
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8
test/CodeGen/Hexagon/absaddr-store.ll
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@ -10,7 +10,7 @@
@d = external global i64
define zeroext i8 @absStoreByte() nounwind {
; CHECK: memb(##b1){{ *}}={{ *}}r{{[0-9]+}}
; CHECK: memb(##b1) = r{{[0-9]+}}
entry:
%0 = load i8, i8* @b0, align 1
%conv = zext i8 %0 to i32
@ -21,7 +21,7 @@ entry:
}
define signext i16 @absStoreHalf() nounwind {
; CHECK: memh(##c1){{ *}}={{ *}}r{{[0-9]+}}
; CHECK: memh(##c1) = r{{[0-9]+}}
entry:
%0 = load i16, i16* @c0, align 2
%conv = sext i16 %0 to i32
@ -32,7 +32,7 @@ entry:
}
define i32 @absStoreWord() nounwind {
; CHECK: memw(##a1){{ *}}={{ *}}r{{[0-9]+}}
; CHECK: memw(##a1) = r{{[0-9]+}}
entry:
%0 = load i32, i32* @a0, align 4
%mul = mul nsw i32 100, %0
@ -41,7 +41,7 @@ entry:
}
define void @absStoreDouble() nounwind {
; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}}
; CHECK: memd(##d) = r{{[0-9]+}}:{{[0-9]+}}
entry:
store i64 100, i64* @d, align 8
ret void

4
test/CodeGen/Hexagon/absimm.ll
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@ -3,7 +3,7 @@
; with immediate value.
define i32 @f1(i32 %i) nounwind {
; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}}
; CHECK: memw(##786432) = r{{[0-9]+}}
entry:
store volatile i32 %i, i32* inttoptr (i32 786432 to i32*), align 262144
ret i32 %i
@ -11,7 +11,7 @@ entry:
define i32* @f2(i32* nocapture %i) nounwind {
entry:
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##786432)
; CHECK: r{{[0-9]+}} = memw(##786432)
%0 = load volatile i32, i32* inttoptr (i32 786432 to i32*), align 262144
%1 = inttoptr i32 %0 to i32*
ret i32* %1

2
test/CodeGen/Hexagon/addr-calc-opt.ll
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@ -4,7 +4,7 @@
; calculation.
;
; CHECK: r0 = memub(r{{[0-9]+}}<<#3{{ *}}+{{ *}}##the_global+516)
; CHECK: r0 = memub(r{{[0-9]+}}<<#3+##the_global+516)
%0 = type { [3 x %1] }
%1 = type { %2, i8, i8, i8, i8, i8, [4 x i8], i8, [10 x i8], [10 x i8], [10 x i8], i8, [3 x %4], i16, i16, i16, i16, i32, i8, [4 x i8], i8, i8, i8, i8, %5, i8, i8, i8, i8, i8, i16, i8, i8, i8, i16, i16, i8, i8, [2 x i8], [2 x i8], i8, i8, i8, i8, i8, i16, i16, i8, i8, i8, i8, i8, i8, %9, i8, [6 x [2 x i8]], i16, i32, %10, [28 x i8], [4 x %17] }

2
test/CodeGen/Hexagon/always-ext.ll
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@ -7,7 +7,7 @@
; CHECK: {
; CHECK-NOT: call abort
; CHECK: memw(##0)
; CHECK: memw(r{{[0-9+]}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##4)
; CHECK: memw(r{{[0-9+]}}<<#2+##4)
; CHECK: }
%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111 = type { i8*, void (%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*)*, i32, i32, i8*, [23 x i32]* }

3
test/CodeGen/Hexagon/bit-loop.ll
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@ -1,10 +1,9 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK-DAG: memh(r{{[0-9]+}}+#0) = r{{[0-9]+}}
; CHECK-DAG: memh(r{{[0-9]+}}+#2) = r{{[0-9]+}}.h
; CHECK-DAG: memh(r{{[0-9]+}}+#4) = r{{[0-9]+}}
; CHECK-DAG: memh(r{{[0-9]+}}+#6) = r{{[0-9]+}}.h
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon"
; Function Attrs: nounwind

4
test/CodeGen/Hexagon/builtin-prefetch-offset.ll
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@ -1,6 +1,6 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check for the immediate offset. It must be a multiple of 8.
; CHECK: dcfetch({{.*}}+{{ *}}#8)
; CHECK: dcfetch({{.*}}+#8)
; In 6.2 (which supports v4+ only), we generate indexed dcfetch in all cases
; (unlike in 6.1, which supported v2, where dcfetch did not allow an immediate
; offset).
@ -9,7 +9,7 @@
; possible one). Check for #0 anyways, if the test fails with a false
; positive, the second check can be eliminated, or rewritten, and in the
; meantime it can help catch real problems.
; CHECK: dcfetch({{.*}}+{{ *}}#0)
; CHECK: dcfetch({{.*}}+#0)
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon"

16
test/CodeGen/Hexagon/cext-check.ll
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@ -2,10 +2,10 @@
; Check that we constant extended instructions only when necessary.
define i32 @cext_test1(i32* %a) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##8000)
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000)
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##4092)
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300)
; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+##8000)
; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},##300000)
; CHECK-NOT: r{{[0-9]+}} = memw(r{{[0-9]+}}+##4092)
; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},##300)
entry:
%0 = load i32, i32* %a, align 4
%tobool = icmp ne i32 %0, 0
@ -29,10 +29,10 @@ return:
}
define i32 @cext_test2(i8* %a) nounwind {
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+{{ *}}##1023)
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000)
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}##1024)
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##6000)
; CHECK-NOT: r{{[0-9]+}} = memub(r{{[0-9]+}}+##1023)
; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},##300000)
; CHECK: r{{[0-9]+}} = memub(r{{[0-9]+}}+##1024)
; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},##6000)
entry:
%tobool = icmp ne i8* %a, null
br i1 %tobool, label %if.then, label %if.end

4
test/CodeGen/Hexagon/cext-valid-packet2.ll
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@ -2,8 +2,8 @@
; Check that the packetizer generates valid packets with constant
; extended add and base+offset store instructions.
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}},{{ *}}##200000)
; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}##12000){{ *}}={{ *}}r{{[0-9]+}}.new
; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},##200000)
; CHECK-NEXT: memw(r{{[0-9]+}}+##12000) = r{{[0-9]+}}.new
; CHECK-NEXT: }
define void @test(i32* nocapture %a, i32* nocapture %b, i32 %c) nounwind {

2
test/CodeGen/Hexagon/cext.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: memub(r{{[0-9]+}}{{ *}}<<{{ *}}#1{{ *}}+{{ *}}##a)
; CHECK: memub(r{{[0-9]+}}<<#1+##a)
@a = external global [5 x [2 x i8]]

2
test/CodeGen/Hexagon/cexti16.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: memuh(r{{[0-9]+}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##a)
; CHECK: memuh(r{{[0-9]+}}<<#2+##a)
@a = external global [5 x [2 x i16]]

8
test/CodeGen/Hexagon/cmp-to-genreg.ll
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@ -2,7 +2,7 @@
; Check that we generate compare to general register.
define i32 @compare1(i32 %a) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}#120)
; CHECK: r{{[0-9]+}} = cmp.eq(r{{[0-9]+}},#120)
entry:
%cmp = icmp eq i32 %a, 120
%conv = zext i1 %cmp to i32
@ -10,7 +10,7 @@ entry:
}
define i32 @compare2(i32 %a) nounwind readnone {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}#120)
; CHECK: r{{[0-9]+}} = !cmp.eq(r{{[0-9]+}},#120)
entry:
%cmp = icmp ne i32 %a, 120
%conv = zext i1 %cmp to i32
@ -18,7 +18,7 @@ entry:
}
define i32 @compare3(i32 %a, i32 %b) nounwind readnone {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
; CHECK: r{{[0-9]+}} = cmp.eq(r{{[0-9]+}},r{{[0-9]+}})
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
@ -26,7 +26,7 @@ entry:
}
define i32 @compare4(i32 %a, i32 %b) nounwind readnone {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
; CHECK: r{{[0-9]+}} = !cmp.eq(r{{[0-9]+}},r{{[0-9]+}})
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32

8
test/CodeGen/Hexagon/cmp-to-predreg.ll
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@ -2,7 +2,7 @@
; Check that we generate compare to predicate register.
define i32 @compare1(i32 %a, i32 %b) nounwind {
; CHECK: p{{[0-3]}}{{ *}}={{ *[!]?}}cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
; CHECK: p{{[0-3]}} = {{!?}}cmp.eq(r{{[0-9]+}},r{{[0-9]+}})
entry:
%cmp = icmp ne i32 %a, %b
%add = add nsw i32 %a, %b
@ -12,7 +12,7 @@ entry:
}
define i32 @compare2(i32 %a) nounwind {
; CHECK: p{{[0-3]}}{{ *}}={{ *[!]?}}cmp.eq(r{{[0-9]+}},{{ *}}#10)
; CHECK: p{{[0-3]}} = {{!?}}cmp.eq(r{{[0-9]+}},#10)
entry:
%cmp = icmp ne i32 %a, 10
%add = add nsw i32 %a, 10
@ -22,7 +22,7 @@ entry:
}
define i32 @compare3(i32 %a, i32 %b) nounwind {
; CHECK: p{{[0-3]}}{{ *}}={{ *}}cmp.gt(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
; CHECK: p{{[0-3]}} = cmp.gt(r{{[0-9]+}},r{{[0-9]+}})
entry:
%cmp = icmp sgt i32 %a, %b
%sub = sub nsw i32 %a, %b
@ -32,7 +32,7 @@ entry:
}
define i32 @compare4(i32 %a) nounwind {
; CHECK: p{{[0-3]}}{{ *}}={{ *}}cmp.gt(r{{[0-9]+}},{{ *}}#10)
; CHECK: p{{[0-3]}} = cmp.gt(r{{[0-9]+}},#10)
entry:
%cmp = icmp sgt i32 %a, 10
%sub = sub nsw i32 %a, 10

6
test/CodeGen/Hexagon/gp-plus-offset-load.ll
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@ -6,7 +6,7 @@
@foo = common global %struct.struc zeroinitializer, align 4
define void @loadWord(i32 %val1, i32 %val2, i32* nocapture %ival) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##foo{{ *}}+{{ *}}4)
; CHECK: r{{[0-9]+}} = memw(##foo+4)
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end
@ -21,7 +21,7 @@ if.end: ; preds = %if.then, %entry
}
define void @loadByte(i32 %val1, i32 %val2, i8* nocapture %ival) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(##foo{{ *}}+{{ *}}1)
; CHECK: r{{[0-9]+}} = memub(##foo+1)
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end
@ -36,7 +36,7 @@ if.end: ; preds = %if.then, %entry
}
define void @loadHWord(i32 %val1, i32 %val2, i16* %ival) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(##foo{{ *}}+{{ *}}2)
; CHECK: r{{[0-9]+}} = memuh(##foo+2)
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end

4
test/CodeGen/Hexagon/gp-plus-offset-store.ll
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@ -6,7 +6,7 @@
@foo = common global %struct.struc zeroinitializer, align 4
define void @storeByte(i32 %val1, i32 %val2, i8 zeroext %ival) nounwind {
; CHECK: memb(##foo{{ *}}+{{ *}}1){{ *}}={{ *}}r{{[0-9]+}}
; CHECK: memb(##foo+1) = r{{[0-9]+}}
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end
@ -20,7 +20,7 @@ if.end: ; preds = %if.then, %entry
}
define void @storeHW(i32 %val1, i32 %val2, i16 signext %ival) nounwind {
; CHECK: memh(##foo{{ *}}+{{ *}}2){{ *}}={{ *}}r{{[0-9]+}}
; CHECK: memh(##foo+2) = r{{[0-9]+}}
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end

6
test/CodeGen/Hexagon/gp-rel.ll
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@ -7,9 +7,9 @@
define i32 @foo(i32 %p) #0 {
entry:
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(gp+#a)
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(gp+#b)
; CHECK: if{{ *}}(p{{[0-3]}}) memw(##c){{ *}}={{ *}}r{{[0-9]+}}
; CHECK: r{{[0-9]+}} = memw(gp+#a)
; CHECK: r{{[0-9]+}} = memw(gp+#b)
; CHECK: if (p{{[0-3]}}) memw(##c) = r{{[0-9]+}}
%0 = load i32, i32* @a, align 4
%1 = load i32, i32* @b, align 4
%add = add nsw i32 %1, %0

12
test/CodeGen/Hexagon/idxload-with-zero-offset.ll
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@ -4,7 +4,7 @@
; load word
define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i32, i32* %a, i32 %tmp
@ -15,7 +15,7 @@ entry:
; load unsigned half word
define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
; CHECK: r{{[0-9]+}} = memuh(r{{[0-9]+}}+r{{[0-9]+}}<<#1)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i16, i16* %a, i32 %tmp
@ -26,7 +26,7 @@ entry:
; load signed half word
define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
; CHECK: r{{[0-9]+}} = memh(r{{[0-9]+}}+r{{[0-9]+}}<<#1)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i16, i16* %a, i32 %tmp
@ -38,7 +38,7 @@ entry:
; load unsigned byte
define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0)
; CHECK: r{{[0-9]+}} = memub(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i8, i8* %a, i32 %tmp
@ -49,7 +49,7 @@ entry:
; load signed byte
define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0)
; CHECK: r{{[0-9]+}} = memb(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i8, i8* %a, i32 %tmp
@ -61,7 +61,7 @@ entry:
; load doubleword
define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3)
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+r{{[0-9]+}}<<#3)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i64, i64* %a, i32 %tmp

252
test/CodeGen/Hexagon/memops.ll
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File diff suppressed because it is too large Load Diff

4
test/CodeGen/Hexagon/memops1.ll
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@ -4,7 +4,7 @@
define void @f(i32* %p) nounwind {
entry:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1
; CHECK: memw(r{{[0-9]+}}+#40) -= #1
%p.addr = alloca i32*, align 4
store i32* %p, i32** %p.addr, align 4
%0 = load i32*, i32** %p.addr, align 4
@ -17,7 +17,7 @@ entry:
define void @g(i32* %p, i32 %i) nounwind {
entry:
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1
; CHECK: memw(r{{[0-9]+}}+#40) -= #1
%p.addr = alloca i32*, align 4
%i.addr = alloca i32, align 4
store i32* %p, i32** %p.addr, align 4

4
test/CodeGen/Hexagon/memops2.ll
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@ -4,7 +4,7 @@
define void @f(i16* nocapture %p) nounwind {
entry:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1
; CHECK: memh(r{{[0-9]+}}+#20) -= #1
%add.ptr = getelementptr inbounds i16, i16* %p, i32 10
%0 = load i16, i16* %add.ptr, align 2
%conv2 = zext i16 %0 to i32
@ -16,7 +16,7 @@ entry:
define void @g(i16* nocapture %p, i32 %i) nounwind {
entry:
; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1
; CHECK: memh(r{{[0-9]+}}+#20) -= #1
%add.ptr.sum = add i32 %i, 10
%add.ptr1 = getelementptr inbounds i16, i16* %p, i32 %add.ptr.sum
%0 = load i16, i16* %add.ptr1, align 2

4
test/CodeGen/Hexagon/memops3.ll
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@ -4,7 +4,7 @@
define void @f(i8* nocapture %p) nounwind {
entry:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1
; CHECK: memb(r{{[0-9]+}}+#10) -= #1
%add.ptr = getelementptr inbounds i8, i8* %p, i32 10
%0 = load i8, i8* %add.ptr, align 1
%conv = zext i8 %0 to i32
@ -16,7 +16,7 @@ entry:
define void @g(i8* nocapture %p, i32 %i) nounwind {
entry:
; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1
; CHECK: memb(r{{[0-9]+}}+#10) -= #1
%add.ptr.sum = add i32 %i, 10
%add.ptr1 = getelementptr inbounds i8, i8* %p, i32 %add.ptr.sum
%0 = load i8, i8* %add.ptr1, align 1

6
test/CodeGen/Hexagon/multi-cycle.ll
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@ -1,12 +1,12 @@
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
; CHECK: v{{[0-9]+}}.h{{ *}}={{ *}}vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
; CHECK: v{{[0-9]+}}.h = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
; CHECK: }
; CHECK: {
; CHECK: v{{[0-9]+}}{{ *}}={{ *}}valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
; CHECK: }
; CHECK: {
; CHECK: v{{[0-9]+}}{{ *}}={{ *}}valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
target triple = "hexagon"

6
test/CodeGen/Hexagon/pic-jumptables.ll
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@ -1,8 +1,8 @@
; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add({{pc|PC}}{{ *}},{{ *}}##
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
; CHECK: r{{[0-9]+}} = add({{pc|PC}},##
; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2)
; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},r{{[0-9]+}})
define i32 @test(i32 %y) nounwind {

6
test/CodeGen/Hexagon/pic-regusage.ll
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@ -5,7 +5,7 @@
; R14, R15 and R28).
; CHECK: call __save_r16_through_r27
; CHECK: }
; CHECK: r14{{ *}}=
; CHECK: r14 =
@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
@ -29,7 +29,7 @@ declare i32 @printf(i8*, ...) #0
; Same as above for R15.
; CHECK: call __save_r16_through_r27
; CHECK: }
; CHECK: r15{{ *}}=
; CHECK: r15 =
; Function Attrs: nounwind optsize
define i32 @_Z7testR15Pi(i32* nocapture %res) #0 {
@ -48,7 +48,7 @@ entry:
; Same as above for R28.
; CHECK: call __save_r16_through_r27
; CHECK: }
; CHECK: r28{{ *}}=
; CHECK: r28 =
; Function Attrs: nounwind optsize
define i32 @_Z7testR28Pi(i32* nocapture %res) #0 {

2
test/CodeGen/Hexagon/postinc-load.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; Check that post-increment load instructions are being generated.
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}++{{ *}}#4{{ *}})
; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}++#4)
define i32 @sum(i32* nocapture %a, i16* nocapture %b, i32 %n) nounwind {
entry:

4
test/CodeGen/Hexagon/postinc-offset.ll
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@ -2,8 +2,8 @@
; RUN: < %s | FileCheck %s
; CHECK: {
; CHECK: ={{ *}}memd([[REG0:(r[0-9]+)]]{{ *}}++{{ *}}#8)
; CHECK-NOT: memw([[REG0]]{{ *}}+{{ *}}#0){{ *}}=
; CHECK: = memd([[REG0:(r[0-9]+)]]++#8)
; CHECK-NOT: memw([[REG0]]+#0) =
; CHECK: }
define void @main() #0 {

2
test/CodeGen/Hexagon/postinc-store.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; Check that post-increment store instructions are being generated.
; CHECK: memw(r{{[0-9]+}}{{ *}}++{{ *}}#4{{ *}}){{ *}}={{ *}}r{{[0-9]+}}
; CHECK: memw(r{{[0-9]+}}++#4) = r{{[0-9]+}}
define i32 @sum(i32* nocapture %a, i16* nocapture %b, i32 %n) nounwind {
entry:

4
test/CodeGen/Hexagon/pred-gp.ll
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@ -7,8 +7,8 @@
; Function Attrs: nounwind
define i32 @test2(i8 zeroext %a, i8 zeroext %b) #0 {
; CHECK: if{{ *}}({{!*}}p{{[0-3]+}}{{[.new]*}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}memw(##{{[cd]}})
; CHECK: if{{ *}}({{!*}}p{{[0-3]+}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}memw(##{{[cd]}})
; CHECK: if ({{!?}}p{{[0-3]+}}{{(.new)?}}) r{{[0-9]+}} = memw(##{{[cd]}})
; CHECK: if ({{!?}}p{{[0-3]+}}) r{{[0-9]+}} = memw(##{{[cd]}})
entry:
%cmp = icmp eq i8 %a, %b
br i1 %cmp, label %if.then, label %entry.if.end_crit_edge

4
test/CodeGen/Hexagon/pred-instrs.ll
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@ -1,8 +1,8 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; Check that we are able to predicate instructions.
; CHECK: if{{ *}}({{!*}}p{{[0-3]}}{{[.new]*}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}{{and|aslh}}
; CHECK: if{{ *}}({{!*}}p{{[0-3]}}{{[.new]*}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}{{and|aslh}}
; CHECK: if ({{!?}}p{{[0-3]}}{{(.new)?}}) r{{[0-9]+}} = {{and|aslh}}
; CHECK: if ({{!?}}p{{[0-3]}}{{(.new)?}}) r{{[0-9]+}} = {{and|aslh}}
@a = external global i32
@d = external global i32

2
test/CodeGen/Hexagon/vec-pred-spill1.ll
View File

@ -3,7 +3,7 @@
; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}}
; CHECK: call puts
; CHECK: call print_vecpred
; CHECK: v{{[0-9]+}}{{ *}}={{ *}}vmem(r{{[0-9]+}}+#3)
; CHECK: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#3)
target triple = "hexagon"

4
test/CodeGen/Hexagon/vect/vect-truncate.ll
View File

@ -23,7 +23,7 @@ polly.loop_header: ; preds = %polly.loop_after45,
br i1 %0, label %polly.loop_body, label %do.cond
polly.loop_body: ; preds = %polly.loop_header
%p_25 = call i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32 undef)
%p_25 = call i32 @llvm.hexagon.A2.asrh(i32 undef)
%1 = insertelement <4 x i32> undef, i32 %p_25, i32 3
%2 = trunc <4 x i32> %1 to <4 x i16>
store <4 x i16> %2, <4 x i16>* undef, align 8
@ -39,4 +39,4 @@ polly.loop_body44: ; preds = %polly.loop_header43
br label %polly.loop_header43
}
declare i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32) nounwind readnone
declare i32 @llvm.hexagon.A2.asrh(i32) nounwind readnone