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Remove the writeback flag from ARM's address mode 4. Now that we have separate

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instructions for ld/st with writeback, the flag is completely redundant.

llvm-svn: 98643
This commit is contained in:
Bob Wilson 2010-03-16 17:46:45 +00:00
parent 92cb518b94
commit 279818d473
8 changed files with 11 additions and 23 deletions
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11
lib/Target/ARM/ARMAddressingModes.h
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@ -463,20 +463,13 @@ namespace ARM_AM {
// IB - Increment before
// DA - Decrement after
// DB - Decrement before
//
// If the 4th bit (writeback)is set, then the base register is updated after
// the memory transfer.
static inline AMSubMode getAM4SubMode(unsigned Mode) {
return (AMSubMode)(Mode & 0x7);
}
static inline unsigned getAM4ModeImm(AMSubMode SubMode, bool WB = false) {
return (int)SubMode | ((int)WB << 3);
}
static inline bool getAM4WBFlag(unsigned Mode) {
return (Mode >> 3) & 1;
static inline unsigned getAM4ModeImm(AMSubMode SubMode) {
return (int)SubMode;
}
//===--------------------------------------------------------------------===//

2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -950,7 +950,7 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
// Set bit W(21)
if (ARM_AM::getAM4WBFlag(MO.getImm()))
if (IsUpdating)
Binary |= 0x1 << ARMII::W_BitShift;
// Set registers

6
lib/Target/ARM/ARMInstrInfo.td
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@ -909,7 +909,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_Br,
"ldm${addr:submode}${p}\t$addr, $dsts",
"ldm${addr:submode}${p}\t$addr!, $dsts",
"$addr.addr = $wb", []>;
// On non-Darwin platforms R9 is callee-saved.
@ -1354,7 +1354,7 @@ def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_iLoadm,
"ldm${addr:submode}${p}\t$addr, $dsts",
"ldm${addr:submode}${p}\t$addr!, $dsts",
"$addr.addr = $wb", []>;
} // mayLoad, hasExtraDefRegAllocReq
@ -1367,7 +1367,7 @@ def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$srcs, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_iStorem,
"stm${addr:submode}${p}\t$addr, $srcs",
"stm${addr:submode}${p}\t$addr!, $srcs",
"$addr.addr = $wb", []>;
} // mayStore, hasExtraSrcRegAllocReq

4
lib/Target/ARM/ARMInstrThumb.td
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@ -549,7 +549,7 @@ def tLDM : T1I<(outs),
def tLDM_UPD : T1It<(outs tGPR:$wb),
(ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
IIC_iLoadm,
"ldm${addr:submode}${p}\t$addr, $dsts",
"ldm${addr:submode}${p}\t$addr!, $dsts",
"$addr.addr = $wb", []>,
T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
} // mayLoad, hasExtraDefRegAllocReq
@ -558,7 +558,7 @@ let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def tSTM_UPD : T1It<(outs tGPR:$wb),
(ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops),
IIC_iStorem,
"stm${addr:submode}${p}\t$addr, $srcs",
"stm${addr:submode}${p}\t$addr!, $srcs",
"$addr.addr = $wb", []>,
T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189

4
lib/Target/ARM/ARMInstrThumb2.td
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@ -1218,7 +1218,7 @@ def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops), IIC_iLoadm,
"ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts",
"ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
"$addr.addr = $wb", []> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
@ -1244,7 +1244,7 @@ def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$srcs, variable_ops),
IIC_iStorem,
"stm${addr:submode}${p}${addr:wide}\t$addr, $srcs",
"stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
"$addr.addr = $wb", []> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;

3
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -505,7 +505,6 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
if (MI->getOperand(i).getReg() == Base)
return false;
}
assert(!ARM_AM::getAM4WBFlag(MI->getOperand(1).getImm()));
Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
} else {
// VLDM{D|S}, VSTM{D|S} addressing mode 5 ops.
@ -573,7 +572,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
.addReg(Base, getKillRegState(BaseKill));
if (isAM4) {
// [t2]LDM_UPD, [t2]STM_UPD
MIB.addImm(ARM_AM::getAM4ModeImm(Mode, true))
MIB.addImm(ARM_AM::getAM4ModeImm(Mode))
.addImm(Pred).addReg(PredReg);
} else {
// VLDM[SD}_UPD, VSTM[SD]_UPD

2
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -524,8 +524,6 @@ void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
O << ".w";
} else {
printOperand(MI, Op);
if (ARM_AM::getAM4WBFlag(MO2.getImm()))
O << "!";
}
}

2
lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
View File

@ -232,8 +232,6 @@ void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
O << ".w";
} else {
printOperand(MI, OpNum);
if (ARM_AM::getAM4WBFlag(MO2.getImm()))
O << "!";
}
}