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Use "NoItineraries" for processors with no itineraries.

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This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.

llvm-svn: 158963
This commit is contained in:
Andrew Trick 2012-06-22 03:58:51 +00:00
parent 3efab18404
commit 279bd30bbc
6 changed files with 44 additions and 46 deletions
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3
include/llvm/Target/TargetSchedule.td
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@ -133,7 +133,8 @@ class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp,
}
// NoItineraries - A marker that can be used by processors without schedule
// info.
// info. Subtargets using NoItineraries can bypass the scheduler's
// expensive HazardRecognizer because no reservation table is needed.
def NoItineraries : ProcessorItineraries<[], [], []>;
// Processor itineraries with non-unit issue width. This allows issue

2
lib/Target/ARM/ARM.td
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@ -141,7 +141,7 @@ def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
FeatureAvoidPartialCPSR]>;
class ProcNoItin<string Name, list<SubtargetFeature> Features>
: Processor<Name, GenericItineraries, Features>;
: Processor<Name, NoItineraries, Features>;
// V4 Processors.
def : ProcNoItin<"generic", []>;

2
lib/Target/ARM/ARMSchedule.td
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@ -258,8 +258,6 @@ def IIC_VTBX4 : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
def GenericItineraries : ProcessorItineraries<[], [], []>;
include "ARMScheduleV6.td"
include "ARMScheduleA8.td"
include "ARMScheduleA9.td"

2
lib/Target/MBlaze/MBlaze.td
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@ -50,7 +50,7 @@ def FeatureSqrt : SubtargetFeature<"sqrt", "HasSqrt", "true",
// MBlaze processors supported.
//===----------------------------------------------------------------------===//
def : Processor<"mblaze", MBlazeGenericItineraries, []>;
def : Processor<"mblaze", NoItineraries, []>;
def : Processor<"mblaze3", MBlazePipe3Itineraries, []>;
def : Processor<"mblaze5", MBlazePipe5Itineraries, []>;

5
lib/Target/MBlaze/MBlazeSchedule.td
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@ -39,11 +39,6 @@ def IIC_BRl : InstrItinClass;
def IIC_WDC : InstrItinClass;
def IIC_Pseudo : InstrItinClass;
//===----------------------------------------------------------------------===//
// MBlaze generic instruction itineraries.
//===----------------------------------------------------------------------===//
def MBlazeGenericItineraries : ProcessorItineraries<[], [], []>;
//===----------------------------------------------------------------------===//
// MBlaze instruction itineraries for three stage pipeline.
//===----------------------------------------------------------------------===//

34
utils/TableGen/SubtargetEmitter.cpp
View File

@ -422,15 +422,18 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
// Get processor itinerary name
const std::string &Name = Proc->getName();
// Skip default
if (Name == "NoItineraries") continue;
// Create and expand processor itinerary to cover all itinerary classes
std::vector<InstrItinerary> ItinList;
ItinList.resize(NItinClasses);
// Get itinerary data list
std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
std::vector<InstrItinerary> ItinList;
// Add an empty itinerary.
if (ItinDataList.empty()) {
ProcList.push_back(ItinList);
continue;
}
// Expand processor itinerary to cover all itinerary classes
ItinList.resize(NItinClasses);
// For each itinerary data
for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
@ -559,8 +562,6 @@ EmitProcessorData(raw_ostream &OS,
const std::string &Name = Itin->getName();
// Skip default
if (Name == "NoItineraries") continue;
// Begin processor itinerary properties
OS << "\n";
OS << "static const llvm::InstrItineraryProps " << Name << "Props(\n";
@ -570,14 +571,16 @@ EmitProcessorData(raw_ostream &OS,
EmitItineraryProp(OS, Itin, "HighLatency", ' ');
OS << ");\n";
// For each itinerary class
std::vector<InstrItinerary> &ItinList = *ProcListIter++;
if (!ItinList.empty()) {
assert(ItinList.size() == ItinClassList.size() && "bad itinerary");
// Begin processor itinerary table
OS << "\n";
OS << "static const llvm::InstrItinerary " << Name << "Entries"
<< "[] = {\n";
// For each itinerary class
std::vector<InstrItinerary> &ItinList = *ProcListIter++;
assert(ItinList.size() == ItinClassList.size() && "bad itinerary");
for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
InstrItinerary &Intinerary = ItinList[j];
@ -593,18 +596,19 @@ EmitProcessorData(raw_ostream &OS,
Intinerary.FirstOperandCycle << ", " <<
Intinerary.LastOperandCycle << " }";
}
OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n";
}
// End processor itinerary table
OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n";
OS << "};\n";
}
OS << '\n';
OS << "static const llvm::InstrItinerarySubtargetValue "
<< Name << " = {\n";
OS << " &" << Name << "Props,\n";
if (ItinList.empty())
OS << " 0\n";
else
OS << " " << Name << "Entries\n";
OS << "};\n";
}